nir: Rename num_shared to shared_size
[mesa.git] / src / intel / common / gen_l3_config.c
2020-06-22 Rafael Antognolliintel/l3: Return the URB size from devinfo for DG1
2020-06-22 Anuj Phogatintel/l3: Add DG1 L3 configuration
2020-06-22 Jordan Justenintel/l3: Allow platforms to have no l3 configurations
2020-06-22 Jordan Justenintel/l3: Don't rely on cfg entry URB size being 0...
2020-04-18 Albert Astals CidFix promotion of floats to doubles
2020-02-01 Anuj Phogatintel/gen12+: Set way_size_per_bank to 4
2019-09-06 Anuj Phogatintel/gen12: Add L3 configurations
2019-08-28 Jordan Justenintel/l3: Don't assert on gen12 (use gen11 config tempo...
2018-11-26 Anuj Phogatintel/icl: Set way_size_per_bank to 4
2018-11-26 Anuj Phogati965/icl: Fix L3 configurations
2018-03-22 Anuj Phogatintel/common/icl: Add L3 config
2018-03-02 Francisco Jerezintel/l3: Don't allocate SLM partition on ICL+.
2017-06-20 Ben Widawskyi965/cnl: Add l3 configuration for Cannonlake
2017-06-20 Anuj Phogati965: Add a variable for way size per bank in get_l3_wa...
2017-06-20 Anuj Phogati965: Fix broxton 2x6 l3 config
2017-06-09 Anuj Phogati965/cnl: Handle gen10 in switch cases across the driver
2017-06-07 Anuj Phogatintel: Fix broxton 2x6 way size computation
2017-06-02 Anuj Phogati965: Simplify l3 way size computations
2016-10-05 Ben Widawskyi965/l3: Add explicit way size calculation for bxt
2016-09-03 Jason Ekstrandintel: Pull the guts of gen7_l3_state.c into a shared...