lima: fix PIPE_CAP_* to mark features that aren't supported yet

lima doesn't support alpha test, flat shading, two-sided color nor
clip planes. We can enable these caps when corresponding hw features
are implemented in the driver.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Tested-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>

lima: implement polygon offset

Fixes some of dEQP-GLES2.functional.polygon_offset.* tests and shadows in Q3A.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Tested-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>

lima: fix viewport clipping

Apparently Mali4x0 doesn't do viewport clipping, so anything rendered beyond viewport
is still rendered. Looks like we need to use scissors to do clipping.

Fixes most of dEQP-GLES2.functional.clipping.*, 6 out of 7 remaining failures
fail on blob as well. Remaining [1] fails on many other gallium drivers.

[1] dEQP-GLES2.functional.clipping.triangle_vertex.clip_three.clip_neg_x_neg_z_and_pos_x_pos_z_and_neg_x_neg_y_pos_z

Suggested-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Tested-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>

lima: fix PLBU_CMD_PRIMITIVE_SETUP command

Apparently it doesn't depend on primitive type, the value
only depends on whether we specify point size via PLBU command --
bit 12 is set in this case

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Tested-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>

glsl: fix potential bug in nir uniform linker

The state value of main_uniform_storage_index will be wrong for
add_parameter() when find_and_update_previous_uniform_storage()
finds a uniform if there is more than 1 uniform used in
multiple shader stages.

The new code is also simpler.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>

etnaviv: add deqp debug option

This new debug option will fake some driver CAPs to be able to run dEQP
for GLES3.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3351>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3351>

aco/wave32: Set the definitions of v_cmp instructions to the lane mask.

The output of v_cmp instructions is s1 (a single SGPR) in wave32 mode,
as opposed to s2 (an SGPR-pair) in wave64 mode.
A couple of cases where this should have been fixed were omitted from
the previous patch by mistake.

Fixes: e0bcefc3a0a15a8c7ec00cfa53fd8fffcc07342a
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>

pan/midgard: Support indirect UBO offsets

...in case we have arrays in a UBO block that we'd like to access
indirectly.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3352>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3352>

intel/fs: Make implied_mrf_writes() an fs_inst method.

This will be convenient in a later commit enabling SIMD32 fragment
shaders, and happens to fix the calculation for MATH instructions
which is currently inaccurate for SIMD-lowered instructions on Gen4-5
platforms (all of them on Gen4 in SIMD16 mode), since it was based on
the shader's dispatch width rather than on the actual execution size
of the instruction.

This causes some shader-db noise on Gen4 due to the more compact
register allocation interacting with the SEND dependency workarounds,
but otherwise no major changes.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/fs/cse: Fix non-deterministic behavior due to inaccurate liveness calculation.

The liveness calculation done by the local CSE pass in order to prune
AEB entries whose sources are no longer live is currently inaccurate,
because the live intervals are calculated once at the beginning of the
pass, so they don't take into account any of the copy instructions
inserted by the CSE pass as it makes progress.  However the IP counter
used in that calculation is based on the start_ip of the basic block,
which is updated automatically whenever any instructions are inserted
into the CFG.  This causes the IP counter and liveness intervals to
get out of sync in programs with multiple basic blocks, causing the
CSE pass to toss AEB entries prematurely, which can lead to missed
optimization opportunities rather non-deterministically.

On BDW this leads to the following shader-db changes:

 total instructions in shared programs: 14952488 -> 14951763 (-0.00%)
 instructions in affected programs: 45416 -> 44691 (-1.60%)
 helped: 40
 HURT: 4

 total spills in shared programs: 20989 -> 20970 (-0.09%)
 spills in affected programs: 103 -> 84 (-18.45%)
 helped: 3
 HURT: 0

 total fills in shared programs: 24981 -> 24926 (-0.22%)
 fills in affected programs: 127 -> 72 (-43.31%)
 helped: 3
 HURT: 0

In addition it avoids a number of regressions in combination with some
of the optimization changes I'm working on for SIMD32, which would
have made CSE more effective...  Causing it to be less effective
elsewhere in the program astonishingly.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/fs: Fix nir_intrinsic_load_barycentric_at_sample for SIMD32.

For uniform sample ID, only the first channel of msg_data will be
initialized.  We need to pass that component only to the SEND message
for SIMD lowering to unzip the descriptor source correctly.

Fixes several dozens of conformance test failures with SIMD32 fragment
shaders enabled, including:

dEQP-GLES31.functional.shaders.multisample_interpolation.interpolate_at_sample.dynamic_sample_number.*

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/fs/gen8+: Fix r127 dst/src overlap RA workaround for EOT message payload.

The problem occured when the return payload of a SIMD8 SEND
instruction was re-used as source payload of an EOT SEND message.  In
such cases the interference edge added by that workaround between the
payload and grf127_send_hack_node would have no effect, because the
payload would be allocated to a fixed range of registers containing
r127 by the special handling of EOT message payloads in the same
function.  This would cause things to blow up if the source payload of
the first SIMD8 message ended up being allocated to a range which
happened to overlap the destination.

Fix it by avoiding r127 altogether in the allocation of EOT message
payloads.

The problem can be reproduced on ICL with the fp-indirections2 Piglit
test-case in combination with the other optimizer changes of this
series.

Fixes: 232ed8980217 "i965/fs: Register allocator shoudn't use grf127 for sends dest"
Cc: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/fs/gen11+: Handle ROR/ROL in lower_simd_width().

Prevents invalid code from being emitted for ROR/ROL instructions in
SIMD32 shaders.

The problem can be reproduced with the following tests while forcing
SIMD32 to be used for fragment shaders:

 piglit.shaders.glsl-rotate-left
 piglit.shaders.glsl-rotate-right

However the issue could occur in production already with compute
shaders and a workgroup size large enough to trigger SIMD32 dispatch.

Fixes: 83fdec0f0de "intel/compiler: Enable the emission of ROR/ROL instructions"
Cc: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

glsl: Fix software 64-bit integer to 32-bit float conversions.

The current implementation was broken for any integers between 2^24
and 2^30 (it would return zero for me on ICL).  The reason is that for
such integers we wouldn't take the 'if (0 <= shiftCount)' early return
path, however 'shiftCount + 7' would be positive, leading to a
negative 'count' argument passed to __shift64RightJamming(), which
would give undefined results.

This reworks the affected conversion functions to use either
__shortShift64Left() or __shift64RightJamming() based on the sign of
the final shift count, which should avoid the problem.  In addition
this should qualify as a clean-up/optimization -- This implementation
of the conversion functions translates to 7 instructions less than the
original on Intel hardware.

This fixes the 'KHR-GL46.shader_ballot_tests.ShaderBallotFunctionBallot'
conformance tests on soft fp64 hardware with large enough subgroup
size (>16).

Fixes: d5cf6e92b4f7 "glsl: Add built-in functions to do uint64_to_fp32(uint64_t)"
Fixes: c9d333a6b76e "glsl: Add built-in functions to do int64_to_fp32(int64_t)"
Cc: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>

aco: compact aco::span<T> to use uint16_t offset and size instead of pointer and size_t.

This reduces the size of the Instruction base class
from 40 bytes to 16 bytes. No pipelinedb changes.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3332>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3332>

aco: compact various Instruction classes

No pipelinedb changes.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3332>

mesa/st: fix a memory leak in get_version

This patch prevents memory leak in get_version function in st_manager.c
This issue was found by valgrind:
16 bytes in 1 blocks are definitely lost in loss record 6 of 1,418
   at 0x483CD99: calloc (in /usr/lib/x86_64-linux-gnu/valgrind/vgpreload_memcheck-amd64-linux.so)
   by 0x63D9476: st_init_extensions (st_extensions.c:1679)
   by 0x63B803B: get_version (st_manager.c:1271)
   by 0x63B8124: st_api_query_versions (st_manager.c:1289)
   by 0x63266EF: dri_init_screen_helper (dri_screen.c:583)
   by 0x6321B12: dri2_init_screen (dri2.c:2110)
   by 0x631AACC: driCreateNewScreen2 (dri_util.c:155)
   by 0x5D58192: dri3_create_screen (dri3_glx.c:897)
   by 0x5D39829: AllocAndFetchScreenConfigs (glxext.c:815)
   by 0x5D39C57: __glXInitialize (glxext.c:941)
   by 0x5D3290A: GetGLXPrivScreenConfig (glxcmds.c:174)
   by 0x5D34F38: glXQueryExtensionsString (glxcmds.c:1307)

Fixes: eca8032f20d0970184843d98e2bddb688e94a3a9 ("gallium: Add ARB_gl_spirv support")
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3345>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3345>

freedreno/drm: Fix memory leak in softpin implementation

Free the memory allocated for cmds/reloc_bos array when destoying the
associated ringbuffer.

For similar fix for the non-softpin implementation see:
https://gitlab.freedesktop.org/mesa/mesa/commit/d014af98b7afc69f4f733c8b8b6f2e3438e68407

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2324
Fixes: f3cc0d2 ("freedreno: import libdrm_freedreno + redesign submit")
Signed-off-by: Lasse Lopperi <lasse.lopperi@ge.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3342>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3342>

aco: limit register usage for large work groups

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>

ac/llvm: Fix ac_build_reduce in wave32 mode.

Previously, when cluster_size was set to 0, it always worked as if
the cluster size was 64. This commit fixes it in wave32 mode by
changing to work as if the cluster size was set to 32.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radeonsi: release saved resources in si_compute_do_clear_or_copy

Fixes: 9b331e462e5 ("radeonsi: use compute shaders for clear_buffer & copy_buffer")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: release saved resources in si_compute_clear_12bytes_buffer

Fixes: 6c901f06752 ("radeonsi: use compute shader for clear 12-byte buffer")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: release saved resources in si_compute_copy_image

Fixes: 1b25d340b79 ("radeonsi: use compute for resource_copy_region when possible")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: release saved resources in si_compute_clear_render_target

Fixes: 984fd735152 ("radeonsi: use compute for clear_render_target when possible")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: release saved resources in si_compute_expand_fmask

Fixes: 095a58204d9 ("radeonsi: expand FMASK before MSAA image stores are used")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: release saved resources in si_retile_dcc

Fixes: 1f21396431a ("radeonsi: add support for displayable DCC for multi-RB chips")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2330
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

main: fix coverity error in _mesa_program_resource_find_name()

We did not take into account if name is NULL, so we could dereference
a NULL pointer in strncmp() call.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

panfrost: Add negative lod bias support

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

virgl/drm: update UAPI

This seems to compile. Header copied over from drm-misc-next
7da5492739db.

Acked-by: Eric Engestrom <eric@engestrom.ch>

lima: drop support for R8G8B8 format

We can only sample from 24-bit packed format and can't render into it and
it causes chromium-based browsers to fail when they create FBO with GL_RGB
format. Drop R8G8B8 alltogether so mesa can promote it to RGBX format.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>

anv: Re-use flush_descriptor_sets in flush_compute_state

There's no reason to hand-roll all of the memory re-allocation fall-back
code for compute shaders.  It's  just duplicated complexity.  This also
makes it more clear in flush_compute_state where the
MEDIA_INTERFACE_DESCRIPTOR_LOAD command gets emitted relative to other
packets in the command stream.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>

anv: Flag descriptors dirty when gl_NumWorkgroups is used

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>

anv: Don't add dynamic state base address to push constants on Gen7

Because Gen7 push constants are already relative to dynamic state base
address, they aren't really an address.  It's deceptive to return an
address from the helper function.  Instead, let's leave it as a
special-case in the gen7-11 helper; we don't need the helper for code
de-duplication for Gen7 anyway.

Fixes: 67d2cb3e9367a "anv: Add get_push_range_address() helper"
Closes: #2323
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>

lima: add debug flag to disable tiling

Add debug flag to disable tiling. Note that it prevents lima from creating
tiled buffers, but it's still able to import them if modifier is specified

Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>

lima: use linear layout for shared buffers if modifier is not specified

Use linear layout for shared buffers if modifier is not specified
and use linear layout when importing buffers with invalid modifier.

Fixes: 01a451b04d2d ("lima: handle DRM_FORMAT_MOD_INVALID in resource_from_handle()")
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>

glsl: call calculate_subroutine_compat() from the nir linker

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

glsl: move calculate_subroutine_compat() to shared linker code

We will make use of this in the nir linker in the following patch.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

glsl: call uniform resource checks from the nir linker

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

glsl: move uniform resource checks into the common linker code

We will call this from the nir linker in the following patch.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

glsl: call check_subroutine_resources() from the nir linker

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

glsl: move check_subroutine_resources() into the shared util code

We will make use of this in the nir linker in the following patch.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

genxml: Remove a non-existant HW bit

ir3: Set up full/half register conflicts correctly

Setting up transitive conflicts between a full register and its two
half registers (eg r0.x and hr0.x and hr0.y) will make the half
registers conflict.  They don't actually conflict and this prevents us
from using both at the same time.

Add and use a new ra helper that sets up transitive conflicts between
a register and its subregisters, except it carefully avoids the
subregister conflict.

Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>

llvmpipe: add ARB_derivative_control support

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

radeonsi/gfx9: force the micro tile mode for MSAA resolve correctly on gfx9

Fixes: 69ea473 "amd/addrlib: update to the latest version"
Closes: #2325
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

anv: fix intel perf queries availability writes

The availability is not written at the location changed in
ee6fbb95a74d...

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: ee6fbb95a74d ("anv: Properly handle host query reset of performance queries")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

docs: Add release notes for 19.3.2, update calendar and home page

docs: add SHA256 sums for 19.3.2

docs: Add release notes for 19.3.2

radeon/vcn: Handle crop parameters for encoder

Set proper cropping parameter if frame cropping is enabled

Signed-off-by: Satyajit Sahu <satyajit.sahu@amd.com>
Reviewed-by: Boyuan Zhang boyuan.zhang@amd.com
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3328>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3328>

nir: fix printing of var_decl with more than 4 components.

Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Fixes: a8ec4082a41830cf67a4fd405402fd2d820722fd ('nir+vtn: vec8+vec16 support')
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3320>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3320>

radv: advertise VK_AMD_shader_image_load_store_lod

This extension allows to use LOD with image read/write operations.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

aco: handle nir_intrinsic_image_deref_{load,store} with lod

Use image_load_mip and image_store_mip respectively if the lod
parameter isn't zero.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

amd/llvm: handle nir_intrinsic_image_deref_{load,store} with lod

Use image_load_mip and image_store_mip respectively if the lod
parameter isn't zero.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

spirv,nir: add new lod parameter to image_{load,store} intrinsics

SPV_AMD_shader_image_load_store_lod allows to use a lod parameter
with OpImageRead, OpImageWrite and OpImageSparseRead.

According to the specification, this parameter should be a 32-bit
integer. It is initialized to 0 when no lod parameter is found
during SPIR-V->NIR translation.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

spirv: add SpvCapabilityImageReadWriteLodAMD

New SPIR-V capability for SPV_AMD_shader_image_load_store_lod.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

mesa: create program resource hash in a single place

This is a cleanup but also a fix for commit dd09f1d806b. In case of
i965 we did not actually create hash for cached shader programs.

Fixes: dd09f1d806b "mesa/st/i965: add a ProgramResourceHash for quicker resource lookup"
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

llvmpipe: add support for ARB_indirect_parameters.

This just adds support for getting the draw count from the
indirect buffer.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3234>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3234>

llvmpipe: enable driver side multi draw indirect

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3234>

gallium/util: add multi_draw_indirect to util_draw_indirect.

ARB_indirect_parameters needs drivers to deal with mutli_draw_indirect
themselves.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3234>

mesa: Prevent _MaxLevel from being less than zero

When decoding using VDPAU, the _MaxLevel value becomes -1 due to
NumLevels being equal to 0 at a certain point, and decoding fails
due to an assertion later on.

Signed-off-by: Thong Thai <thong.thai@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Cc: 19.2 19.3 <mesa-stable@lists.freedesktop.org>

ac: add ac_build_s_endpgm

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

ac: add 128-bit bitcount

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

ac/gpu_info: add pc_lines and use it in radeonsi

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

ac: unify primitive export code

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

ac: unify build_sendmsg_gs_alloc_req

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

radeonsi: clean up messy si_emit_rasterizer_prim_state

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

radeonsi: determine accurately if line stippling is enabled for performance

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

radeonsi: test polygon mode enablement accurately

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

radeonsi: fix context roll tracking in si_emit_shader_vs

probably harmless, because we don't need to track context rolls on gfx10

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

radeonsi: fix monolithic pixel shaders with two-sided colors and SampleMaskIn

They are never used except for testing AMD_DEBUG=mono.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

ac/gpu_info: always use distributed tessellation on gfx10

This might fix a hang on Navi14.

Cc: 19.2 19.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

gallium: bypass u_vbuf if it's not needed (no fallbacks and no user VBOs)

This decreases CPU overhead, because u_vbuf is completely bypassed
in those cases.

Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

gallium/cso_context: move non-vbuf vertex buffer and element code into helpers

These will be reused.

Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

gallium: put u_vbuf_get_caps return values into u_vbuf_caps

Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

etnaviv: remove unnecessary vertex_elements_state_create error checking

PIPE_CAP_MAX_VERTEX_BUFFERS already sets the maximum vertex_buffer_index.

There's no need to error on num_elements == 0 (if that can even happen).

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

etnaviv: implement gl_VertexID/gl_InstanceID

Fixes:
dEQP-GLES3.functional.instanced.*

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

etnaviv: HALTI2+ instanced draw

Fixes:
dEQP-GLES3.functional.draw.draw_arrays_instanced.*
dEQP-GLES3.functional.draw.draw_elements_instanced.*

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

etnaviv: update headers from rnndb

Update to etna_viv commit 46af5f1d.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

anv: don't close invalid syncfd semaphore

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

gallium/swr: Fix glVertexPointer race condition.

Sometimes using user buffer (not VBO) e.g. glVertexPointer
one thread could free memory before other thread used it.
Instead of copying this memory to driver simplier thing is
to block until draw finish.

Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>

intel/disasm: Fix decoding of src0 of SENDS

There is no instruction field for the register file for src0 because
it's always GRF.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3309>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3309>

meta: Add cleanup function for Bitmap

Buffer object and temporary texture were never freed, causing memory leaks.

Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

nir/spirv: skip unreachable blocks in Phi second pass

Only the blocks that are reachable are inserted with an end_nop
instruction at the end.

When handling the Phi second pass, if the Phi has a parent block that
does not have an end_nop then it means this block is unreachable, and
thus we can ignore it, as the Phi will never come through it.

Fixes dEQP-VK.graphicsfuzz.uninit-element-cast-in-loop.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>

radeonsi: check ctx->sdma_cs before using it

e5167a9276de1f383888714b41d3a9be2b9c1da9 disabled SDMA for gfx8.
This caused 3 piglit arb_sparse_buffer tests (basic, buffer-data
and commit) to crash on GFX8.

Reported-by: Michel Dänzer <michel@daenzer.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Fixes: e5167a9276d ("radeonsi: disable SDMA on gfx8 to fix corruption on RX 580")

radv: do not fill keys from fragment shader twice

radv_fill_shader_info() already does that.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

main: allow external textures for BindImageTexture

From issue 10 of the OES_EGL_image_external_essl3:

  A limited set of use-cases is enabled by making glBindImageTexture
  accept external textures. Shaders can access such external textures
  using the existing <image2D> sampler type.

Fixes: 02a6d901eee ("mesa: add OES_EGL_image_external_essl3 support")
Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

intel/nir: Add a memory barrier before barrier()

Our barrier instruction does not implicitly do a memory fence but the
GLSL barrier() intrinsic is supposed to.  The easiest back-portable
solution is to just add the NIR barriers.  We'll sort this out more
properly in later commits.

Cc: mesa-stable@lists.freedesktop.org
Closes: #2138
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>

radv: Emit a BATCH_BREAK when changing pixel shaders or CB_TARGET_MASK.

Fixes a hang on Raven with Resident Evil 2.

I did not find anything more restricted to fix it:

- Setting persistent_states_per_bin to 1 fixes it too,
  but likely does an internal break on any descriptor set changes
  too.
- Only breaking the batch when cb_target_mask changes does not fix
  it (and looking at AMDVLK comments, I suspect the code in radeonsi
  should really be doing a FLUSH_DFSM).
- Always doing a FLUSH_DFSM on shader switch helps, but that is more
  often than this and I don't think we should be doing that when DFSM
  is disabled.
- Also emitting the existing break on framebuffer change when DFSM is
  disabled does not fix the issue.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2315
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

mesa/st/i965: add a ProgramResourceHash for quicker resource lookup

Many resource APIs require searching by name, add a hash table to make
this faster. Currently we traverse the whole resource list for name
based queries, this change makes all these cases use the hash.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2203
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3254>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3254>

gitlab-ci: Test against LLVM / clang 9 on x86

They're not available for Debian buster yet, so we have to use upstream
snapshot packages again.

In contrast to earlier, we now store the LLVM APT repository key in Git
instead of re-downloading it every time.

panfrost: Don't double-flip Z/W for 2D arrays

We need to mindful that we don't clobber the shadow comparator.

Fixes dEQP-GLES3.functional.shaders.texture_functions.texture.sampler2darrayshadow_*

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>

pan/midgard: Account for z/w flip in texelFetch

Required for proper txf of 2D arrays.

Fixes dEQP-GLES3.functional.shaders.texture_functions.texelfetch.*2darray*

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>

panfrost: Adjust for mismatch between hardware/Gallium in arrays/cube

The hardware separates face selection and array indexing, it looks like,
whereas Gallium smushes them together with some modulus fun. Let's fix
it so mipmapped 2D arrays work without regressing cubemaps.

Fixes dEQP-GLES3.functional.texture.filtering.2d_array.* among others.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>

panfrost: Respect constant buffer_offset

Fixes dEQP-GLES3.functional.ubo.multi_basic_types.single_buffer.* among
others

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>

glsl: use nir version of check_image_resources() for nir linker

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>

glsl: add check_image_resources() for the nir linker

This is adapted from the GLSL IR code but doesn't need to
iterate over the IR. I believe this also fixes a potential bug in
the GLSL IR code which potentially counts the same output twice.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>

glsl: use nir linker to link atomics

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>

mesa: add new UseNIRGLSLLinker constant

This will be used to disable some GLSL IR passes in following
patches.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>

glsl: reorder link_and_validate_uniforms() calls

This is required for the following commit.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>