mesa.git
22 months agoutil/hash_table: update users to use new optimal integer hash functions
Anthony Pesch [Thu, 16 Jan 2020 14:11:16 +0000 (09:11 -0500)]
util/hash_table: update users to use new optimal integer hash functions

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3475>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3475>

22 months agoutil/hash_table: added hash functions for integer types
Anthony Pesch [Sat, 18 Jan 2020 06:38:31 +0000 (01:38 -0500)]
util/hash_table: added hash functions for integer types

A few hash_table users roll their own integer hash functions which
call _mesa_hash_data to perform the hashing which ultimately calls
into XXH32 with a dynamic key length. When using small keys with a
constant size the hash rate can be greatly improved by inlining
XXH32 and providing it a constant key length, see:
https://fastcompression.blogspot.com/2018/03/xxhash-for-small-keys-impressive-power.html

Additionally, this patch removes calls to _mesa_key_hash_string and
makes them instead call _mesa_has_string directly, matching the new
integer hash functions.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3475>

22 months agoutil/hash_table: replace _mesa_hash_data's fnv1a hash function with xxhash
Anthony Pesch [Sat, 18 Jan 2020 05:54:10 +0000 (00:54 -0500)]
util/hash_table: replace _mesa_hash_data's fnv1a hash function with xxhash

For most key sizes, xxhash outperforms fnv1a's hash rate substantially (bug
2153). In particular, the V3D driver hashes multiple ~200 byte keys as part
of the shader cache lookup which can easily eat up 10-20% of the runtime on
the Raspberry Pi. Swapping over to xxhash drops this to ~1% of the runtime.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3475>

22 months agoutil: move fnv1a hash implementation into its own header
Anthony Pesch [Sat, 18 Jan 2020 05:51:42 +0000 (00:51 -0500)]
util: move fnv1a hash implementation into its own header

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3475>

22 months agoutil: import xxhash
Anthony Pesch [Sat, 18 Jan 2020 05:47:19 +0000 (00:47 -0500)]
util: import xxhash

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3475>

22 months agowinsys/amdgpu: Close KMS handles for other DRM file descriptions
Michel Dänzer [Mon, 23 Dec 2019 17:59:10 +0000 (18:59 +0100)]
winsys/amdgpu: Close KMS handles for other DRM file descriptions

When a BO or amdgpu_screen_winsys is destroyed.

Should fix leaking such BOs in other DRM file descriptions.

v2:
* Pass the correct file descriptor to drmIoctl (Pierre-Eric
  Pelloux-Prayer)
* Use _mesa_hash_table_remove
v3:
* Close handles in amdgpu_winsys_unref as well
v4:
* Adapt to amdgpu_winsys::sws_list_lock.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2270
Fixes: 11a3679e3aba "winsys/amdgpu: Make KMS handles valid for original
                     DRM file descriptor"

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3202>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3202>

22 months agowinsys/amdgpu: Re-use amdgpu_screen_winsys when possible
Michel Dänzer [Mon, 6 Jan 2020 17:47:41 +0000 (18:47 +0100)]
winsys/amdgpu: Re-use amdgpu_screen_winsys when possible

Namely, if os_same_file_description determined that the DRM file
descriptor references the same file description.

v2:
* Adapt to amdgpu_winsys::sws_list_lock.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3202>

22 months agoutil: Add os_same_file_description helper
Michel Dänzer [Mon, 6 Jan 2020 17:24:52 +0000 (18:24 +0100)]
util: Add os_same_file_description helper

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3202>

22 months agowinsys/amdgpu: Only re-export KMS handles for different DRM FDs
Michel Dänzer [Mon, 23 Dec 2019 17:51:57 +0000 (18:51 +0100)]
winsys/amdgpu: Only re-export KMS handles for different DRM FDs

When the amdgpu_screen_winsys uses the same FD as the amdgpu_winsys
(which is always the case for the first amdgpu_screen_winsys), we can
just use bo->u.real.kms_handle.

v2:
* Also only create the kms_handles hash table if the
  amdgpu_screen_winsys fd is different from the amdgpu_winsys one.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3202>

22 months agowinsys/amdgpu: Keep track of retrieved KMS handles using hash tables
Michel Dänzer [Mon, 30 Sep 2019 16:00:50 +0000 (18:00 +0200)]
winsys/amdgpu: Keep track of retrieved KMS handles using hash tables

The assumption being that KMS handles are only retrieved for relatively
few BOs, so hash tables should be efficient both in terms of performance
and memory consumption.

We use the address of struct amdgpu_winsys_bo as the key and its
kms_handle field (the KMS handle valid for the DRM file descriptor
passed to amdgpu_device_initialize) as the hash value.

v2:
* Add comment above amdgpu_screen_winsys::kms_handles (Pierre-Eric
  Pelloux-Prayer)
v3:
* Protect kms_handles hash table with amdgpu_winsys::sws_list_lock
  mutex.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3202>

22 months agowinsys/amdgpu: Keep a list of amdgpu_screen_winsyses in amdgpu_winsys
Michel Dänzer [Mon, 30 Sep 2019 16:36:06 +0000 (18:36 +0200)]
winsys/amdgpu: Keep a list of amdgpu_screen_winsyses in amdgpu_winsys

v2:
* Add dedicated mutex for the list.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3202>

22 months agoaco: implement nir_op_f2i64/nir_op_f2u64 on GFX6
Samuel Pitoiset [Tue, 21 Jan 2020 08:13:46 +0000 (09:13 +0100)]
aco: implement nir_op_f2i64/nir_op_f2u64 on GFX6

V_TRUNC_F64 and V_FLOOR_F64 needs to be lowered on GFX6.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3477>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3477>

22 months agoaco: implement 64-bit nir_op_ffloor on GFX6
Samuel Pitoiset [Mon, 20 Jan 2020 08:00:07 +0000 (09:00 +0100)]
aco: implement 64-bit nir_op_ffloor on GFX6

GFX6 doesn't have V_FLOOR_F64, it needs to be lowered. Loosely based
on the AMDGPU LLVM backend.

Introduce a new function because it will be useful for some other
64-bit operations.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3477>

22 months agoaco: implement 64-bit nir_op_fround_even on GFX6
Samuel Pitoiset [Tue, 21 Jan 2020 07:57:07 +0000 (08:57 +0100)]
aco: implement 64-bit nir_op_fround_even on GFX6

GFX6 doesn't have V_RNDNE_F64, it needs to be lowered. Loosely based
on the AMDGPU LLVM backend.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3477>

22 months agoaco: implement 64-bit nir_op_fceil on GFX6
Samuel Pitoiset [Tue, 21 Jan 2020 07:16:59 +0000 (08:16 +0100)]
aco: implement 64-bit nir_op_fceil on GFX6

GFX6 doesn't have V_CEIL_F64, it needs to be lowered. Loosely based
on the AMDGPU LLVM backend.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3477>

22 months agoaco: implement 64-bit nir_op_ftrunc on GFX6
Samuel Pitoiset [Mon, 20 Jan 2020 17:39:57 +0000 (18:39 +0100)]
aco: implement 64-bit nir_op_ftrunc on GFX6

GFX6 doesn't have V_TRUNC_F64, it needs to be lowered. Loosely based
on the AMDGPU LLVM backend.

Introduce a new function because it will be useful for some other
64-bit operations.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3477>

22 months agoaco: implement nir_intrinsic_global_atomic_* on GFX6
Samuel Pitoiset [Fri, 17 Jan 2020 15:11:55 +0000 (16:11 +0100)]
aco: implement nir_intrinsic_global_atomic_* on GFX6

GFX6 doesn't have FLAT instructions, use MUBUF instructions instead.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3477>

22 months agoaco: implement nir_intrinsic_load_global on GFX6
Samuel Pitoiset [Fri, 17 Jan 2020 14:14:41 +0000 (15:14 +0100)]
aco: implement nir_intrinsic_load_global on GFX6

GFX6 doesn't have FLAT instructions, use MUBUF instructions instead.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3477>

22 months agoaco: implement nir_intrinsic_store_global on GFX6
Samuel Pitoiset [Fri, 17 Jan 2020 12:22:16 +0000 (13:22 +0100)]
aco: implement nir_intrinsic_store_global on GFX6

GFX6 doesn't have FLAT instructions, use MUBUF instructions instead.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3477>

22 months agoaco: fix wrong IR in nir_intrinsic_load_barycentric_at_sample
Samuel Pitoiset [Tue, 21 Jan 2020 08:47:18 +0000 (09:47 +0100)]
aco: fix wrong IR in nir_intrinsic_load_barycentric_at_sample

Only GFX6 was affected, my mistake. The total number of SGPR operands
should be 4 when we want to create a vec4.

Fixes: dbdf3b3ef97 ("aco: implement nir_intrinsic_load_barycentric_at_sample on GFX6")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3477>

22 months agoanv/iris: warn gen12 3DSTATE_HS restriction
Lionel Landwerlin [Tue, 21 Jan 2020 15:54:01 +0000 (17:54 +0200)]
anv/iris: warn gen12 3DSTATE_HS restriction

This should never happen but better off documenting it in case someone
plays with max threads numbers.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3489>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3489>

22 months agogallium/swr: add option for static link
Krzysztof Raszkowski [Wed, 22 Jan 2020 11:26:45 +0000 (12:26 +0100)]
gallium/swr: add option for static link

Set swr-shared to 'false' to link SWR statically into Mesa.
Only one swr arch can be specified if swr-shared is set to false.

Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3510>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3510>

22 months agoaco: fix printing assembly with CLRXdisasm on GFX6
Samuel Pitoiset [Mon, 20 Jan 2020 17:41:00 +0000 (18:41 +0100)]
aco: fix printing assembly with CLRXdisasm on GFX6

We thought that CLRXdisasm allowed gfx600 as well as gfx700 but
it actually doesn't. Use the family for GFX6 chips instead.

Fixes: 0099f85232b ("aco: print assembly with CLRXdisasm for GFX6-GFX7 if found on the system")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3531>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3531>

22 months agoclover/meson: Define OpenCL header macros
Pierre Moreau [Tue, 17 Dec 2019 17:11:10 +0000 (18:11 +0100)]
clover/meson: Define OpenCL header macros

Rather than defining the macros any time right before including an
OpenCL header, set Meson to define them for the whole clover project.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Francisco Jerez <currojerez@riseup.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3137>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3137>

22 months agoclover: Use the dispatch table type from the OpenCL headers
Pierre Moreau [Tue, 17 Dec 2019 16:27:53 +0000 (17:27 +0100)]
clover: Use the dispatch table type from the OpenCL headers

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2243
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3137>

22 months agoinclude/CL: Update OpenCL headers to latest
Pierre Moreau [Tue, 17 Dec 2019 16:23:43 +0000 (17:23 +0100)]
include/CL: Update OpenCL headers to latest

This latest update contains a new header that defines the dispatch table
structure in order to avoid OpenCL implementations having to define it
themselves.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3137>

22 months agoradv: advertise VK_AMD_shader_fragment_mask
Samuel Pitoiset [Thu, 16 May 2019 10:26:16 +0000 (12:26 +0200)]
radv: advertise VK_AMD_shader_fragment_mask

Only for GFX8+ because it's untested on older generations.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3304>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3304>

22 months agoaco: add support for nir_texop_fragment_{mask}_fetch
Samuel Pitoiset [Tue, 7 Jan 2020 14:18:58 +0000 (15:18 +0100)]
aco: add support for nir_texop_fragment_{mask}_fetch

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3304>

22 months agoac/nir: add support for nir_texop_fragment_{mask}_fetch
Samuel Pitoiset [Thu, 16 May 2019 12:43:23 +0000 (14:43 +0200)]
ac/nir: add support for nir_texop_fragment_{mask}_fetch

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3304>

22 months agonir/lower_input_attachments: lower nir_texop_fragment_{mask}_fetch
Samuel Pitoiset [Tue, 7 Jan 2020 09:01:14 +0000 (10:01 +0100)]
nir/lower_input_attachments: lower nir_texop_fragment_{mask}_fetch

These instructions are allowed to fetch from multisampled
subpass input attachments.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3304>

22 months agospirv: add support for SpvOpFragment{Mask}FetchAMD operations
Samuel Pitoiset [Tue, 7 Jan 2020 07:45:24 +0000 (08:45 +0100)]
spirv: add support for SpvOpFragment{Mask}FetchAMD operations

nir_tex_src_ms_index is re-used for the fragment index with
nir_texop_fragment_fetch to avoid introducing a new texture source type.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3304>

22 months agonir: add two new texture ops for multisample fragment color/mask fetches
Samuel Pitoiset [Tue, 7 Jan 2020 07:39:39 +0000 (08:39 +0100)]
nir: add two new texture ops for multisample fragment color/mask fetches

This introduces:
   - nir_texop_fragment_mask_fetch (fetch a fragment mask from a
     compressed multisampled color surface)
   - nir_texop_fragment_fetch (fetch a color fragment for a
     particular sample at corresponding fragment mask index).

These two texture operations are necessary for implementing
SPV_AMD_shader_fragment_mask.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3304>

22 months agospirv: add SpvCapabilityFragmentMaskAMD
Samuel Pitoiset [Thu, 16 May 2019 10:25:40 +0000 (12:25 +0200)]
spirv: add SpvCapabilityFragmentMaskAMD

This new capability is for SPV_AMD_shader_fragment_mask.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3304>

22 months agoradv: handle missing implicit subpass dependencies
Samuel Pitoiset [Thu, 9 Jan 2020 09:55:54 +0000 (10:55 +0100)]
radv: handle missing implicit subpass dependencies

When a subpass doesn't declare an explicit dependency from/to
VK_SUBPASS_EXTERNAL, Vulkan says there is an implicit dependency.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3330>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3330>

22 months agoradv: add explicit external subpass dependencies to meta operations
Samuel Pitoiset [Thu, 9 Jan 2020 09:36:12 +0000 (10:36 +0100)]
radv: add explicit external subpass dependencies to meta operations

No functional changes because a subpass dependency with dstStageMask
set to VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT is a no-op.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3330>

22 months agogallivm: fix find lsb
Dave Airlie [Mon, 20 Jan 2020 04:56:36 +0000 (14:56 +1000)]
gallivm: fix find lsb

the GLSL return value is different than the llvm intrinsic.

Fixes arb gpu shader5 tests

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3528>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3528>

22 months agogalllivm: fix gather offset casting
Dave Airlie [Mon, 20 Jan 2020 03:21:28 +0000 (13:21 +1000)]
galllivm: fix gather offset casting

cast texture offsets to 32-bit integers

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3528>

22 months agollvmpipe: fix some integer instruction lowering.
Dave Airlie [Mon, 20 Jan 2020 03:16:49 +0000 (13:16 +1000)]
llvmpipe: fix some integer instruction lowering.

We want to lower to shifts for bitfields, and lower ifind_msb.

Fixes a bunch of gpu shader5 tests.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3528>

22 months agogallivm: fix gather component handling.
Dave Airlie [Mon, 20 Jan 2020 02:03:23 +0000 (12:03 +1000)]
gallivm: fix gather component handling.

Fixes the extended gather test for gpu shader5

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3528>

22 months agoturnip: Add support for uniform texel buffers.
Eric Anholt [Wed, 22 Jan 2020 20:25:10 +0000 (12:25 -0800)]
turnip: Add support for uniform texel buffers.

Pretty straightforward: Port texture descriptor code from freedreno, fill
in alignment limits from closed vk, and tu_cmd_buffer.c was already
uploading the texture descriptor.

This doesn't implement storage texel buffers (required in the compute
pipeline) yet, since those will need an IBO descriptor for the store path.
Still, making the load path be connected to the texture descriptor won't
hurt.

Part of #2237

Fixes dEQP-VK.binding_model.shader_access.primary_cmd_buf.uniform_texel_buffer.*

Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3522>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3522>

22 months agointel: Fix aux map alignments on 32-bit builds.
Kenneth Graunke [Wed, 22 Jan 2020 00:46:24 +0000 (16:46 -0800)]
intel: Fix aux map alignments on 32-bit builds.

ALIGN() brilliantly uses uintptr_t, making it unsafe for use with 64-bit
GPU addresses in 32-bit builds of the driver.  Use align64() instead,
which uses uint64_t.

Fixes assertion failures when running any 32-bit program on Tigerlake.

Fixes: 2e6a7ced4db ("iris/gen12: Write GFX_AUX_TABLE base address register")
Fixes: 0d0290bb3f7 ("intel/common: Add surface to aux map translation table support")
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3507>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3507>

22 months agoutil: Remove tmp argument from BITSET_FOREACH_SET macro
Matt Turner [Tue, 21 Jan 2020 23:07:24 +0000 (15:07 -0800)]
util: Remove tmp argument from BITSET_FOREACH_SET macro

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3499>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3499>

22 months agoutil: Explain BITSET_FOREACH_SET params
Matt Turner [Tue, 21 Jan 2020 22:48:04 +0000 (14:48 -0800)]
util: Explain BITSET_FOREACH_SET params

__size, in particular, makes this macro rather confusing to understand
how to use. Hopefully this comment saves future users the headache.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3499>

22 months agolima: implement invalidate_resource()
Vasily Khoruzhick [Thu, 5 Dec 2019 03:27:43 +0000 (19:27 -0800)]
lima: implement invalidate_resource()

We don't need to resolve invalidated resources, so it should
improve performance for applications that are doing this hint.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3476>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3476>

22 months agoglsl_to_nir: update interface type properly
Timothy Arceri [Tue, 14 Jan 2020 06:12:06 +0000 (17:12 +1100)]
glsl_to_nir: update interface type properly

Since 76ba225184ed the member variable types were being redefined
but we assigned the old interface type to the variable.

In a following patch series we will use the types to check if we
are dealing with an interface instance when apply GLSL linking
rules.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3468>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3468>

22 months agoglsl: count uniform components and storage better in nir linking
Timothy Arceri [Mon, 13 Jan 2020 05:09:10 +0000 (16:09 +1100)]
glsl: count uniform components and storage better in nir linking

This helps avoid incorrect validation error when linking glsl
shaders and avoids assigning uniform storage slots that will
never be used.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3468>

22 months agoglsl: fix check for matrices in blocks when using nir uniform linker
Timothy Arceri [Mon, 13 Jan 2020 00:36:10 +0000 (11:36 +1100)]
glsl: fix check for matrices in blocks when using nir uniform linker

We need to stripe any arrays before checking the type. Here we
just use the uniform type which has already be stripped.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3468>

22 months agoglsl: remove bogus assert in nir uniform linking
Timothy Arceri [Fri, 10 Jan 2020 11:58:49 +0000 (22:58 +1100)]
glsl: remove bogus assert in nir uniform linking

I'm not sure why this was first added but it causes an assert
on any uniform matrix.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3468>

22 months agonir/algebraic: Optimize some 64-bit integer comparisons involving zero
Ian Romanick [Thu, 28 Nov 2019 00:26:03 +0000 (16:26 -0800)]
nir/algebraic: Optimize some 64-bit integer comparisons involving zero

I noticed that we can do better for these kinds of comparisons while
working on the lowering for iadd_sat@64 and isub_sat@64.  This
eliminated 11 instruction from the fs-addSaturate-int64.shader_test.

My hope is that this will improve the run-time of int64 tests on Ice
Lake.  I have no data to support or refute this.

Unsurprisingly, no changes on shader-db.

v2: Condition the min and max patterns with nir_lower_minmax64.
Suggested by Caio.  Very long discussion in the MR. :)

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>

22 months agoanv: Enable SPV_INTEL_shader_integer_functions2 and VK_INTEL_shader_integer_functions2
Ian Romanick [Thu, 3 Jan 2019 00:07:59 +0000 (16:07 -0800)]
anv: Enable SPV_INTEL_shader_integer_functions2 and VK_INTEL_shader_integer_functions2

Currently only implemented in the scalar backend, so only enable for
Gen8+.  If support for the other opcodes is added to the vec4 backend,
Gen7 could be supported.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>

22 months agoiris: Enable INTEL_shader_integer_functions2
Ian Romanick [Thu, 14 Nov 2019 22:20:48 +0000 (14:20 -0800)]
iris: Enable INTEL_shader_integer_functions2

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>

22 months agogallium: Add a cap bit for integer multiplication between 32-bit and 16-bit
Ian Romanick [Thu, 14 Nov 2019 22:16:26 +0000 (14:16 -0800)]
gallium: Add a cap bit for integer multiplication between 32-bit and 16-bit

Driver supports integer multiplication between a 32-bit integer and a
16-bit integer.  If the second operand is 32-bits, the upper 16-bits are
ignored, and the low 16-bits are possibly sign extended as necessary.

Iris will eventually enable this.  Not sure about other drivers.

v2: Add default value to u_screen.c.  Suggested by Caio.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>

22 months agogallium: Add a cap bit for OpenCL-style extended integer functions
Ian Romanick [Thu, 14 Nov 2019 22:12:30 +0000 (14:12 -0800)]
gallium: Add a cap bit for OpenCL-style extended integer functions

Iris will eventually enable this.  Looking at the header files, it looks
like Midgard could also enable it.  Basically, any GPU that fully
supports OpenCL can.

v2: Add default value to u_screen.c.  Suggested by Caio.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>

22 months agoi965: Enable INTEL_shader_integer_functions2 on Gen8+
Ian Romanick [Tue, 11 Sep 2018 23:50:06 +0000 (16:50 -0700)]
i965: Enable INTEL_shader_integer_functions2 on Gen8+

v2: Use new lower_hadd64 and lower_usub_sat64 flags.

v3: Enable SPIR-V capability.

v4: Move lowering options to COMMON_SCALAR_OPTIONS.  Suggested by Caio.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>

22 months agospirv: Add support for IntegerFunctions2INTEL capability
Ian Romanick [Mon, 24 Sep 2018 13:46:48 +0000 (06:46 -0700)]
spirv: Add support for IntegerFunctions2INTEL capability

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>

22 months agospirv: Silence a bunch of unused parameter warnings
Ian Romanick [Mon, 24 Sep 2018 13:44:38 +0000 (06:44 -0700)]
spirv: Silence a bunch of unused parameter warnings

The change to get_uniform_nir_atomic_op make it look like the other
get_*_nir_atomic_op functions.  The rest just add UNUSED or ASSERTED
to parameters required for some of the interfaces.

src/compiler/spirv/spirv_to_nir.c: In function ‘struct_member_decoration_cb’:
src/compiler/spirv/spirv_to_nir.c:673:47: warning: unused parameter ‘val’ [-Wunused-parameter]
                             struct vtn_value *val, int member,
                                               ^~~
src/compiler/spirv/spirv_to_nir.c: In function ‘struct_member_matrix_stride_cb’:
src/compiler/spirv/spirv_to_nir.c:778:50: warning: unused parameter ‘val’ [-Wunused-parameter]
                                struct vtn_value *val, int member,
                                                  ^~~
src/compiler/spirv/spirv_to_nir.c: In function ‘type_decoration_cb’:
src/compiler/spirv/spirv_to_nir.c:805:61: warning: unused parameter ‘ctx’ [-Wunused-parameter]
                     const struct vtn_decoration *dec, void *ctx)
                                                             ^~~
src/compiler/spirv/spirv_to_nir.c: In function ‘spec_constant_decoration_cb’:
src/compiler/spirv/spirv_to_nir.c:1359:70: warning: unused parameter ‘v’ [-Wunused-parameter]
 spec_constant_decoration_cb(struct vtn_builder *b, struct vtn_value *v,
                                                                      ^
src/compiler/spirv/spirv_to_nir.c: In function ‘handle_workgroup_size_decoration_cb’:
src/compiler/spirv/spirv_to_nir.c:1407:43: warning: unused parameter ‘data’ [-Wunused-parameter]
                                     void *data)
                                           ^~~~
src/compiler/spirv/spirv_to_nir.c: In function ‘vtn_handle_function_call’:
src/compiler/spirv/spirv_to_nir.c:1806:55: warning: unused parameter ‘opcode’ [-Wunused-parameter]
 vtn_handle_function_call(struct vtn_builder *b, SpvOp opcode,
                                                       ^~~~~~
src/compiler/spirv/spirv_to_nir.c:1807:54: warning: unused parameter ‘count’ [-Wunused-parameter]
                          const uint32_t *w, unsigned count)
                                                      ^~~~~
src/compiler/spirv/spirv_to_nir.c: In function ‘get_uniform_nir_atomic_op’:
src/compiler/spirv/spirv_to_nir.c:2548:47: warning: unused parameter ‘b’ [-Wunused-parameter]
 get_uniform_nir_atomic_op(struct vtn_builder *b, SpvOp opcode)
                                               ^
src/compiler/spirv/spirv_to_nir.c: In function ‘vtn_handle_atomics’:
src/compiler/spirv/spirv_to_nir.c:2633:48: warning: unused parameter ‘count’ [-Wunused-parameter]
                    const uint32_t *w, unsigned count)
                                                ^~~~~
src/compiler/spirv/spirv_to_nir.c: In function ‘vtn_handle_barrier’:
src/compiler/spirv/spirv_to_nir.c:3197:48: warning: unused parameter ‘count’ [-Wunused-parameter]
                    const uint32_t *w, unsigned count)
                                                ^~~~~
src/compiler/spirv/spirv_to_nir.c: In function ‘vtn_handle_execution_mode’:
src/compiler/spirv/spirv_to_nir.c:3618:68: warning: unused parameter ‘data’ [-Wunused-parameter]
                           const struct vtn_decoration *mode, void *data)
                                                                    ^~~~

Acked-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>

22 months agonir/spirv: Translate SPIR-V to NIR for new INTEL_shader_integer_functions2 opcodes
Ian Romanick [Fri, 21 Sep 2018 07:35:18 +0000 (00:35 -0700)]
nir/spirv: Translate SPIR-V to NIR for new INTEL_shader_integer_functions2 opcodes

v2: Rebase on 272e927d0e9 ("nir/spirv: initial handling of OpenCL.std
extension opcodes")

v3: Add missing SpvOpUCountTrailingZerosINTEL case to switch in
vtn_handle_body_instruction. Remove stray semicolon in
vtn_nir_alu_op_for_spirv_opcode. Use umin instead of umax for
SpvOpUCountTrailingZerosINTEL "lowering" in vtn_handle_alu.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>

22 months agointel/fs: Implement support for NIR opcodes for INTEL_shader_integer_functions2
Ian Romanick [Tue, 11 Sep 2018 23:49:51 +0000 (16:49 -0700)]
intel/fs: Implement support for NIR opcodes for INTEL_shader_integer_functions2

v2: Remove smashing type to D for nir_op_irhadd.  Caio noticed it was
odd, and removing it fixes an assertion failure in the crucible
func.shader.averageRounded.int64_t test (because the source should be
W).

v3: Emit BRW_OPCODE_MUL directly for nir_op_umul_32x16 and
nir_op_imul_32x16.  Suggested by Curro.

v4: Smash types of MUL instruction generated for nir_op_umul_32x16 and
nir_op_imul_32x16.  With this change, I get the same assembly now as I
did with v2.

v5: Remove support for pre-Gen7.  The integer multiply path was
incorrect, and, since the extension isn't enabled pre-Gen7, there's no
way to test it.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>

22 months agointel/fs: Add SHADER_OPCODE_[IU]SUB_SAT pseudo-ops
Ian Romanick [Wed, 19 Sep 2018 08:28:06 +0000 (01:28 -0700)]
intel/fs: Add SHADER_OPCODE_[IU]SUB_SAT pseudo-ops

v2: Add a big comment explaining the [IU]SUB_SAT lowering.  Suggested by
Caio.

v3: Use get_fpu_lowered_simd_width in get_lowered_simd_width.  Suggested
by Ken on IRC.

v4: Fix a typo in a comment.  Noticed by Caio.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>

22 months agointel/fs: Don't lower integer multiplies that don't need lowering
Ian Romanick [Thu, 5 Dec 2019 16:25:34 +0000 (08:25 -0800)]
intel/fs: Don't lower integer multiplies that don't need lowering

v2: Move the check to fs_visitor::lower_integer_multiplication.
Previously the cases where lowering was skipped, the original
instruction was removed by fs_visitor::lower_integer_multiplication.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>

22 months agocompiler: Translate GLSL IR to NIR for new INTEL_shader_integer_functions2 expressions
Ian Romanick [Thu, 13 Sep 2018 00:05:14 +0000 (17:05 -0700)]
compiler: Translate GLSL IR to NIR for new INTEL_shader_integer_functions2 expressions

v2: Rebase on 272e927d0e9 ("nir/spirv: initial handling of OpenCL.std
extension opcodes")

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>

22 months agonir/algebraic: Add lowering for 64-bit iadd_sat and isub_sat
Ian Romanick [Wed, 27 Nov 2019 21:22:38 +0000 (13:22 -0800)]
nir/algebraic: Add lowering for 64-bit iadd_sat and isub_sat

v2: Rearranged and expand the comment about the optimizations applied to
the lowering.  Suggested by Caio.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>

22 months agonir/algebraic: Add lowering for 64-bit uadd_sat
Ian Romanick [Wed, 27 Nov 2019 20:55:27 +0000 (12:55 -0800)]
nir/algebraic: Add lowering for 64-bit uadd_sat

Fixes piglit fs-addsaturate-uint64 and vs-addsaturate-uint64 on Ice
Lake.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>

22 months agonir/algebraic: Add lowering for 64-bit usub_sat
Ian Romanick [Wed, 19 Sep 2018 08:17:31 +0000 (01:17 -0700)]
nir/algebraic: Add lowering for 64-bit usub_sat

v2: Rebase on 272e927d0e9 ("nir/spirv: initial handling of OpenCL.std
extension opcodes")

v3: Add a new lower_usub_sat64 flag that only applies to the 64-bit
version of the nir_op_usub_sat instruction.

v4: Also enable the lowering when nir_lower_iadd64 is set.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> [v3]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>

22 months agonir/algebraic: Add lowering for 64-bit hadd and rhadd
Ian Romanick [Wed, 19 Sep 2018 08:17:09 +0000 (01:17 -0700)]
nir/algebraic: Add lowering for 64-bit hadd and rhadd

v2: Rebase on 272e927d0e9 ("nir/spirv: initial handling of OpenCL.std
extension opcodes")

v3: Add a new lower_hadd64 flag that only applies to the 64-bit versions
of the instructions.

v4: Also enable the lowering when nir_lower_iadd64 is set.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> [v3]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>

22 months agonir/algebraic: Add lowering for uabs_usub and uabs_isub
Ian Romanick [Tue, 11 Sep 2018 22:38:36 +0000 (15:38 -0700)]
nir/algebraic: Add lowering for uabs_usub and uabs_isub

v2: Remove some rebase failures noticed by Caio.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>

22 months agonir: Add new instructions for INTEL_shader_integer_functions2
Ian Romanick [Tue, 11 Sep 2018 07:13:36 +0000 (00:13 -0700)]
nir: Add new instructions for INTEL_shader_integer_functions2

uctz isn't added because it will implemented in the GLSL path and the
SPIR-V path using other pre-existing instructions.

v2: Avoid signed integer overflow for uabs_isub(0, INT_MIN).  Noticed by
Caio.

v3: Alternate fix for signed integer overflow for abs_sub(0, INT_MIN).
I tried the previous methon in a small test program with -ftrapv, and it
failed.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> [v1]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>

22 months agoglsl: Add built-in functions for INTEL_shader_integer_functions2
Ian Romanick [Tue, 11 Sep 2018 06:17:49 +0000 (23:17 -0700)]
glsl: Add built-in functions for INTEL_shader_integer_functions2

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>

22 months agoglsl_types: Add function to get an unsigned base type from a signed type
Ian Romanick [Mon, 17 Sep 2018 15:53:24 +0000 (08:53 -0700)]
glsl_types: Add function to get an unsigned base type from a signed type

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>

22 months agoglsl: Add new expressions for INTEL_shader_integer_functions2
Ian Romanick [Tue, 11 Sep 2018 05:38:29 +0000 (22:38 -0700)]
glsl: Add new expressions for INTEL_shader_integer_functions2

v2: Re-write iadd64_saturate and isub64_saturate to avoid undefined
overflow behavior.  Also fix copy-and-paste bug in isub64_saturate.
Suggested by Caio.

v3: Avoid signed integer overflow for abs_sub(0, INT_MIN).  Noticed by
Caio.

v4: Alternate fix for signed integer overflow for abs_sub(0, INT_MIN).
I tried the previous methon in a small test program with -ftrapv, and it
failed.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>

22 months agomesa: Extension boilerplate for INTEL_shader_integer_functions2
Ian Romanick [Tue, 11 Sep 2018 00:54:56 +0000 (17:54 -0700)]
mesa: Extension boilerplate for INTEL_shader_integer_functions2

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>

22 months agointel/compiler: Move Gen4/5 rounding to visitor
Matt Turner [Thu, 16 Jan 2020 19:17:14 +0000 (11:17 -0800)]
intel/compiler: Move Gen4/5 rounding to visitor

Gen4/5's rounding instructions operate differently than later Gens'.
They all return the floor of the input and the "Round-increment"
conditional modifier answers whether the result should be incremented by
1.0 to get the appropriate result for the operation (and thus its
behavior is determined by the round opcode; e.g., RNDZ vs RNDE).

Since this requires a second instruciton (a predicated ADD) that
consumes the result of the round instruction, the round instruction
cannot write its result directly to the (write-only) message registers.
By emitting the ADD in the generator, the backend thinks it's safe to
store the round's result directly to the message register file.

To avoid this, we move the emission of the ADD instruction to the NIR
translator so that the backend has the information it needs.

I suspect this also fixes code generated for RNDZ.SAT but since
Gen4/5 don't support GLSL 1.30 which adds the trunc() function, I
couldn't write a piglit test to confirm. My thinking is that if x=-0.5:

      sat(trunc(-0.5)) = 0.0

But on Gen4/5 where sat(trunc(x)) is implemented as

      rndz.r.f0  result, x             // result = floor(x)
                                       // set f0 if increment needed
      (+f0) add  result, result, 1.0   // fixup so result = trunc(x)

then putting saturate on both instructions will give the wrong result.

      floor(-0.5) = -1.0
      sat(floor(-0.5)) = 0.0
      // +1 increment would be needed since floor(-0.5) != trunc(-0.5)
      sat(sat(floor(-0.5)) + 1.0) = 1.0

Fixes: 6f394343b1f ("nir/algebraic: i2f(f2i()) -> trunc()")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2355
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3459>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3459>

22 months agomeson: Do not require libdrm for DRI2 on hurd
Samuel Thibault [Sat, 28 Dec 2019 21:51:39 +0000 (22:51 +0100)]
meson: Do not require libdrm for DRI2 on hurd

Cc: 19.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Signed-off-by: Samuel Thibault <samuel.thibault@ens-lyon.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3231>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3231>

22 months agoutil: Do not fail to build on unknown pthread_setname_np
Samuel Thibault [Sat, 28 Dec 2019 21:06:27 +0000 (22:06 +0100)]
util: Do not fail to build on unknown pthread_setname_np

This is only used for debugging, so better making porting on various systems
less hard.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Samuel Thibault <samuel.thibault@ens-lyon.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3229>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3229>

22 months agoloader: #define PATH_MAX when undefined (eg. Hurd)
Samuel Thibault [Sat, 28 Dec 2019 21:00:57 +0000 (22:00 +0100)]
loader: #define PATH_MAX when undefined (eg. Hurd)

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Samuel Thibault <samuel.thibault@ens-lyon.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3228>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3228>

22 months agoutil/atomic: fix return type of p_atomic_add_return() fallback
Eric Engestrom [Sun, 8 Dec 2019 12:52:21 +0000 (12:52 +0000)]
util/atomic: fix return type of p_atomic_add_return() fallback

Fixes: 385d13f26d2b69db9423 ("util/atomic: Add a _return variant of p_atomic_add")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3012>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3012>

22 months agogallium: dmabuf support for yuv formats that are not natively supported
James Xiong [Thu, 16 Jan 2020 18:19:34 +0000 (10:19 -0800)]
gallium: dmabuf support for yuv formats that are not natively supported

V2 (Kenneth Graunke):
   added a helper function to check if every format is supported

Signed-off-by: James Xiong <james.xiong@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2846>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2846>

22 months agointel/compiler: Return early if read() failed
Emmanuel Gil Peyrot [Wed, 20 Nov 2019 15:21:42 +0000 (16:21 +0100)]
intel/compiler: Return early if read() failed

This was the only warning I could see while compiling Iris.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2821>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2821>

22 months agointel/perf: adapt to platforms like Solaris without d_type in struct dirent
Alan Coopersmith [Wed, 6 Nov 2019 00:56:46 +0000 (16:56 -0800)]
intel/perf: adapt to platforms like Solaris without d_type in struct dirent

Signed-off-by: Alan Coopersmith <alan.coopersmith@oracle.com>
[Eric: factor out the is_dir_or_link() check and fix a bug in v1]
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
v3: include directory path when lstat'ing files
v4: fix inverted check in enumerate_sysfs_metrics()

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2258>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2258>

22 months agollvmpipe: drop LLVM < 3.4 support
Eric Engestrom [Sat, 16 Nov 2019 10:25:21 +0000 (10:25 +0000)]
llvmpipe: drop LLVM < 3.4 support

We don't support < 3.9 anymore, so this code is dead.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2760>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2760>

22 months agoegl: drop confusing mincore() error message
Eric Engestrom [Fri, 27 Dec 2019 20:59:26 +0000 (20:59 +0000)]
egl: drop confusing mincore() error message

A user came to me asking how to fix this error, but it's entirely
expected that `get_wl_surface_proxy()` on recent enough wayland
compositors will always print it.
Let's just remove the message altogether, it is basically never useful.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3219>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3219>

22 months agoaco: fix off-by-one error when initializing sgpr_live_in
Rhys Perry [Wed, 22 Jan 2020 11:51:31 +0000 (11:51 +0000)]
aco: fix off-by-one error when initializing sgpr_live_in

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2394
Fixes: 93c8ebfa780 ('aco: Initial commit of independent AMD compiler')
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3511>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3511>

22 months agoradv: fix double free corruption in radv_alloc_memory()
Samuel Pitoiset [Wed, 22 Jan 2020 07:40:11 +0000 (08:40 +0100)]
radv: fix double free corruption in radv_alloc_memory()

If the driver fails to allocate memory for some reasons, it shouldn't
free the 'mem' object twice.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2302
Fixes: 825ddfee599 ("radv: Handle device memory alloc failure with normal free.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3508>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3508>

22 months agogitlab-ci: Use single if for manual job rules entry
Michel Dänzer [Mon, 20 Jan 2020 17:39:50 +0000 (18:39 +0100)]
gitlab-ci: Use single if for manual job rules entry

I thought multiple ifs would all need to match, but looks like only the
last one (or either one?) does.

This should prevent a manual pipeline from getting created after merging
changes which can't affect the pipeline.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3474>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3474>

22 months agogitlab-ci: Set GIT_STRATEGY to none for the dummy job
Michel Dänzer [Mon, 20 Jan 2020 17:34:34 +0000 (18:34 +0100)]
gitlab-ci: Set GIT_STRATEGY to none for the dummy job

It doesn't need anything from the Git repository.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3474>

22 months agoutil/u_thread: Fix build under Haiku
X512 [Thu, 9 Jan 2020 00:59:21 +0000 (00:59 +0000)]
util/u_thread: Fix build under Haiku

22 months agohaiku/hgl: Fix build via header reordering
Alexander von Gluck IV [Thu, 9 Jan 2020 00:58:31 +0000 (00:58 +0000)]
haiku/hgl: Fix build via header reordering

22 months agoaco: fix operand kill flags when a temporary is used more than once
Rhys Perry [Tue, 21 Jan 2020 14:24:01 +0000 (14:24 +0000)]
aco: fix operand kill flags when a temporary is used more than once

Helps create v_mac_f32 from v_mad_f32(b, a, b)

Totals from affected shaders:
SGPRS: 35824 -> 35824 (0.00 %)
VGPRS: 33460 -> 33456 (-0.01 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 2187264 -> 2180976 (-0.29 %) bytes
LDS: 127 -> 127 (0.00 %) blocks
Max Waves: 3802 -> 3802 (0.00 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3486>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3486>

22 months agopanfrost/midgard: Add missing lowering passes for type/size conversion ops
Boris Brezillon [Mon, 20 Jan 2020 21:02:40 +0000 (22:02 +0100)]
panfrost/midgard: Add missing lowering passes for type/size conversion ops

Replace the manual type/size conversion lowering description by one
that's automatically generated and covers all type/size conversions.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3478>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3478>

22 months agopanfrost/midgard: Add 64 bits float <-> int converters
Boris Brezillon [Mon, 20 Jan 2020 21:05:14 +0000 (22:05 +0100)]
panfrost/midgard: Add 64 bits float <-> int converters

The 64 bit converter cases were missing, add them now.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3478>

22 months agopanfrost/midgard: Fix mir_print_instruction() for branch instructions
Boris Brezillon [Mon, 20 Jan 2020 20:44:49 +0000 (21:44 +0100)]
panfrost/midgard: Fix mir_print_instruction() for branch instructions

Branch instructions should not be treated as regular ALUs.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3478>

22 months agopanfrost/midgard: Add f2f64 support
Boris Brezillon [Mon, 20 Jan 2020 15:05:31 +0000 (16:05 +0100)]
panfrost/midgard: Add f2f64 support

So we can convert floats into doubles.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3478>

22 months agopanfrost/midgard: Factorize f2f and u2u handling
Boris Brezillon [Mon, 20 Jan 2020 15:03:52 +0000 (16:03 +0100)]
panfrost/midgard: Factorize f2f and u2u handling

Those size conversion operations work the same way apart from f2f
using an fmov op code and u2u using an imov. Let's handle them in the
same case block to avoid code duplication.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3478>

22 months agopanfrost/midgard: Make sure promote_fmov() only promotes 32-bit imovs
Boris Brezillon [Mon, 20 Jan 2020 14:55:21 +0000 (15:55 +0100)]
panfrost/midgard: Make sure promote_fmov() only promotes 32-bit imovs

mir_constant_float() assumes we're dealing with 32-bit integers/floats,
which is only the case if reg_mode is equal to midgard_reg_mode_32.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3478>

22 months agopanfrost/midgard: Rework mir_adjust_constants() to make it type/size agnostic
Boris Brezillon [Mon, 20 Jan 2020 14:44:48 +0000 (15:44 +0100)]
panfrost/midgard: Rework mir_adjust_constants() to make it type/size agnostic

Right now, constant combining is not supported in 16 bit mode, and 64
bit mode is simply ignored. Let's rework the function to make it
type/bit-size agnostic.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3478>

22 months agopanfrost/midgard: Use a union to manipulate embedded constants
Boris Brezillon [Mon, 20 Jan 2020 14:00:57 +0000 (15:00 +0100)]
panfrost/midgard: Use a union to manipulate embedded constants

Each instruction bundle can contain up to 16 constant bytes. The meaning
of those byte is instruction dependent: it depends on the instruction
native type (int, uint or float) and the instruction reg_mode (8, 16, 32
or 64 bit). Those different layouts can be exposed as a union to
facilitate constants manipulation.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3478>

22 months agoanv: ensure prog params are initialized with 0s
Lionel Landwerlin [Wed, 22 Jan 2020 13:49:25 +0000 (15:49 +0200)]
anv: ensure prog params are initialized with 0s

As a result of 9baa33cef01f our backend compiler leaves params pretty
much untouched. So in order to avoid storing uninitialized values in
the shader cache blobs, just 0 out this array.

I've considered not even allocating this array which works on gen8+
but the vec4 backend still makes a copy of this array and so it
crashes on memcpy on HSW.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 9baa33cef01f ("anv: Rework push constant handling")
Reported-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3516>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3516>

22 months agopanfrost: Fix crash in compute variant allocation
Alyssa Rosenzweig [Mon, 20 Jan 2020 21:01:53 +0000 (16:01 -0500)]
panfrost: Fix crash in compute variant allocation

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Fixes: d8a3501f1b2 ("panfrost: Dynamically allocate shader variants")
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3515>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3515>

22 months agoetnaviv: drm: Don't miscalculate timeout
Guido Günther [Wed, 22 Jan 2020 10:43:11 +0000 (11:43 +0100)]
etnaviv: drm: Don't miscalculate timeout

The current code overflows (s * 1000000000) for s >= 5 but that is
e.g. used in etna_bo_cpu_prep.

Signed-off-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3509>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3509>

22 months agoegl: Fix _eglPointerIsDereferencable w/o mincore()
Alexander van der Grinten [Sun, 15 Dec 2019 10:25:37 +0000 (11:25 +0100)]
egl: Fix _eglPointerIsDereferencable w/o mincore()

On platforms without mincore(), _eglPointerIsDereferencable()
currently just checks whether p != NULL. This is not sufficient:
In the Wayland platform code (i.e., in get_wl_surface_proxy()),
_eglPointerIsDereferencable() is called on the version field
of `struct wl_egl_window` which is 3 on current versions of
Wayland. This causes a segfault when trying to dereference p.

Fix this behavior by assuming that the first page of the
process is never dereferencable.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3103>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3103>