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intel/tools: Add test for address register as source
2020-02-25 Sagar Ghugeintel/tools: Add test for address register as source
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2020-02-25 Sagar Ghugeintel/tools: Set correct address register file and...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2020-02-25 Sagar Ghugeintel/tools: Handle STATE_REG in typed source operand
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2020-02-25 Sagar Ghugeintel/tools: Handle illegal instruction
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2020-02-13 Sagar Ghugeintel/isl: Switch to R8_UNORM format for compatiblity
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2020-02-13 Sagar Ghugeintel/isl: Move get_format_encoding function to isl
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2020-01-27 Sagar Ghugeintel/compiler: Clear accumulator register before EOT
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-29 Sagar Ghugeintel/isl: Allow stencil buffer to support compression...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-29 Sagar Ghugeiris: Resolve stencil resource prior to copy or used...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-29 Sagar Ghugeiris: Prepare resources before stencil blit operation
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-29 Sagar Ghugeiris: Prepare depth resource if clear_depth enable
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-29 Sagar Ghugeiris: Prepare stencil resource before clear depth stencil
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-29 Sagar Ghugeiris: Resolve stencil buffer lossless compression with...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-29 Sagar Ghugeintel/blorp: Set stencil resolve enable bit
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-29 Sagar Ghugeintel: Track stencil aux usage on Gen12+
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-29 Sagar Ghugeintel/blorp: Add helper function for stencil buffer...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-29 Sagar Ghugeintel/blorp: Assign correct view while clearing depth...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-29 Sagar Ghugegenxml/gen12: Add Stencil Buffer Resolve Enable bit
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-28 Sagar Ghugeiris: Create resource with aux_usage MCS_CCS
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-28 Sagar Ghugeintel/isl: Support lossless compression with multisamples
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-28 Sagar Ghugeiris: Get correct resource aux usage for copy
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-28 Sagar Ghugeintel/blorp: Use isl_aux_usage_has_mcs instead of comparing
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-28 Sagar Ghugeiris: Define MCS_CCS state transitions and usages
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-28 Sagar Ghugeiris: Initialize CCS to fast clear while using with MCS
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-28 Sagar Ghugeintel/isl: Don't reconfigure aux surfaces for MCS
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-22 Sagar Ghugeintel/compiler: Refactor disassembly of sources in...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-22 Sagar Ghugeintel/compiler: Don't move immediate in register
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-22 Sagar Ghugeintel/compiler: Set bits according to source file
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-22 Sagar Ghugeintel/compiler: Add Immediate support for 3 source...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-21 Sagar Ghugeintel: Add missing entry for brw_nir_lower_alpha_to_coverage...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-21 Sagar Ghugeintel/compiler: Remove emit_alpha_to_coverage workaround...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-21 Sagar Ghugenir: Add alpha_to_coverage lowering pass
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-11 Sagar Ghugeintel/eu/gen12: Implement immediate 64 bit constant...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-08-20 Sagar Ghugeiris: Enable non coherent framebuffer fetch on broadwell
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-08-20 Sagar Ghugeiris: Free resource if failed to allocate surface state
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-08-20 Sagar Ghugeiris: Pass isl_surf to fill_surface_state
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-08-20 Sagar Ghugeiris: Add infrastructure to support non coherent framebuffer...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-08-20 Sagar Ghugeiris: Add helper functions to get tile offset
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-08-20 Sagar Ghugeiris: Add helper function to get isl dim layout
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-08-20 Sagar Ghugeiris: Add render target read entry in binding table
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-07-30 Sagar Ghugeiris: Enable EXT_texture_shadow_lod
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-07-30 Sagar Ghugegallium: Add PIPE_CAP_TEXTURE_SHADOW_LOD
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-07-30 Sagar Ghugei965: Enable EXT_texture_shadow_lod
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-07-26 Sagar Ghugenir: Optimize umod lowering
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-07-24 Sagar Ghugenir: Add lowering for nir_op_irem and nir_op_imod
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-07-23 Sagar Ghugeanv: Implement VK_KHR_imageless_framebuffer
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-07-01 Sagar Ghugeintel/tools: Add assembler unit tests for ROL/ROR instructions
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-07-01 Sagar Ghugeintel/tools: Add ROL/ROR support in assembler
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-07-01 Sagar Ghugenir: Add lower_rotate flag and set to true in all drivers
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-07-01 Sagar Ghugeintel/compiler: Emit ROR and ROL instruction
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-07-01 Sagar Ghugenir: Add optimization to use ROR/ROL instructions
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-07-01 Sagar Ghugenir: Add urol and uror opcodes
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-07-01 Sagar Ghugeintel/compiler: Enable the emission of ROR/ROL instructions
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-06-25 Sagar Ghugeglsl: Fix round64 conversion function
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-06-04 Sagar Ghugeintel/compiler: Fix assertions in brw_alu3
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-05-07 Sagar Ghugeintel/disasm: Disassemble immediate value properly...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-05-07 Sagar Ghugeintel/disasm: Disassemble JIP offset for while
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-05-07 Sagar Ghugeintel/compiler: Replicate 16 bit immediate value correctly
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-05-07 Sagar Ghugeintel/compiler: Print quad value in hex format
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-05-07 Sagar Ghugeintel/tools: Add unit tests for assembler
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-05-07 Sagar Ghugeintel/tools: New i965 instruction assembler tool
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-04-12 Sagar Ghugeintel/fs: Remove unused condition from opt_algebraic...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-03-12 Sagar Ghugeiris: Flag fewer dirty bits in BLORP
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-03-08 Sagar Ghugeiris: Track last VS URB entry size
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-03-08 Sagar Ghugeiris: Refactor code to share 3DSTATE_URB_* packet
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-03-04 Sagar Ghugespirv: Allow [i/u]mulExtended to use new nir opcode
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-03-04 Sagar Ghugenir/algebraic: Optimize low 32 bit extraction
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-03-04 Sagar Ghugeglsl: [u/i]mulExtended optimization for GLSL
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-03-04 Sagar Ghugenir/glsl: Add another way of doing lower_imul64 for...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-02-21 Sagar Ghugeiris: Don't allocate a BO per query object
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-01-10 Sagar Ghugeglsl: Add "built-in" functions to do fp32_to_int64...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-01-10 Sagar Ghugeglsl: Add "built-in" functions to do fp32_to_uint64...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-01-10 Sagar Ghugeglsl: Add "built-in" functions to do fp64_to_int64...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-01-10 Sagar Ghugeglsl: Add utility function to round and pack int64_t...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-01-10 Sagar Ghugeglsl: Add "built-in" functions to do fp64_to_uint64...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-01-10 Sagar Ghugeglsl: Add utility function to round and pack uint64_t...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-01-10 Sagar Ghugeglsl: Add "built-in" functions to do int64_to_fp32...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-01-10 Sagar Ghugeglsl: Add "built-in" functions to do uint64_to_fp32...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-01-10 Sagar Ghugeglsl: Add "built-in" functions to do int64_to_fp64...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-01-10 Sagar Ghugeglsl: Add "built-in" functions to do uint64_to_fp64...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2018-12-18 Sagar Ghugenir: Add a new lowering option to lower 3D surfaces...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2018-12-10 Sagar Ghugeintel/compiler: Always print flag subregister number
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2018-12-10 Sagar Ghugeintel/compiler: Set swizzle to BRW_SWIZZLE_XXXX for...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2018-11-15 Sagar Ghugeintel/compiler: Disassemble GEN6_SFID_DATAPORT_SAMPLER_CACHE...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2018-10-26 Sagar Ghugeintel/compiler: Print message descriptor as immediate...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2018-10-26 Sagar Ghugeintel/compiler: Print hex representation along with...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2018-10-23 Sagar Ghugeintel/compiler: Change src1 reg type to unsigned doubleword
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2018-10-04 Sagar Ghugeintel: aubinator: Fix memory leaks
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2018-10-04 Sagar Ghugeintel/decoder: construct correct xml filename
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2018-10-04 Sagar Ghugeintel/decoder: Avoid freeing invalid pointer
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2018-10-04 Sagar Ghugeintel/decoder: add gen_spec_init method
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2018-08-29 Sagar Ghugeintel/tools: new i965_disasm tool
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2018-08-28 Sagar Ghugei965: enable AMD_depth_clamp_separate
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2018-08-28 Sagar Ghugei965: add functional changes for AMD_depth_clamp_separate
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2018-08-28 Sagar Ghugemesa: add EXTRA_EXT for AMD_depth_clamp_separate
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2018-08-28 Sagar Ghugemesa: add support for GL_AMD_depth_clamp_separate tokens
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2018-08-28 Sagar Ghugemesa: Add support for AMD_depth_clamp_separate
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2018-08-28 Sagar Ghugemesa: Add types for AMD_depth_clamp_separate.
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2018-08-28 Sagar Ghugeglapi: define AMD_depth_clamp_separate
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2018-08-27 Sagar Ghugeintel/eu: print bytes instead of 32 bit hex value
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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