3 Tercel is a Wishbone-compatible, 32-bit, single+quad SPI Flash controller with XIP support. Both 3BA and 4BA devices are supported.
5 Tercel provides two interfaces to the host CPU:
6 1. A direct MMIO read/write region for the flash device
7 2. A configuration space where the core can be reconfigured on-line for operation beyond single SPI 3BA mode with fallback clocks (default)
13 On reset, the Tercel core provides read-only access in single SPI, 3BA mode to any attached Flash device. It uses the generic well-known single byte access instructions to provide full XIP support. Host software is responsible for reading the Flash ID of the attached Flash device and reconfiguring the Tercel core for faster and more advanced operating modes. This reconfiguration can take place online, with no interruption to the concurrent read operations in progress on the main MMIO Flash window.
15 By default, with Microwatt, the two bus regions are available at:
16 Flash MMIO (XIP base): 0xf0000000
17 Core configuration: 0xc8050000
22 Set bit 0 of "Core control register 1"
24 - Send Flash ID command
25 Write 0x9e to SPI MMIO base address (offset 0x0)
28 Read four bytes from SPI MMIO base address (offset 0x0) and assemble into 32-bit device ID
29 Read sequence is big endian per Flash device convention
32 Clear bit 0 of "Core control register 1"
36 ## [0x00 - 0x07) Device ID
38 Device make/model unique identifier for PnP functionality
39 Fixed value: 0x7c5250545350494d
41 ## [0x08 - 0x0b) Device version
43 Device revision (stepping)
45 | Bits | Description |
46 |-------|---------------|
47 | 31:16 | Major version |
48 | 15:8 | Minor version |
53 System clock frequency
55 Can be used to set divisor to meet specific SPI Flash clock frequency requirements
59 PHY configuration register 1
62 | Bits | Description |
63 |-------|--------------------------------------------------------------------------------------------------------|
64 | 31:24 | Insert idle cycles with CS deasserted between SPI operations (cycle count to insert, 0 for none) |
66 | 21 | Enable quad I/O data write in QSPI mode |
67 | 20 | Enable quad I/O data read in QSPI mode |
68 | 19 | Enable fast reads (1 == use fast read commands and cycles, 0 == use standard read commands and cycles) |
69 | 18 | Enable 4BA addressing mode (1 == 4BA, 0 == 3BA) |
70 | 17:16 | PHY I/O type (0 == single, 2 == quad, others invalid) |
71 | 15:8 | Dummy cycle count |
72 | 7:0 | SPI clock divisor |
74 Clock divisor works as follows:
75 Clock frequency calculation:
76 spi_clock_frequency = peripheral_bus_clock_frequency / ((spi_clock_divisor - 1) * 2)
78 | Clock divisor value | Actual division |
79 |---------------------|------------------------------------|
80 | 0 | override to standard divide by two |
92 Flash configuration register 1
95 | Bits | Description |
96 |-------|-----------------------|
98 | 23:16 | QSPI 3BA read command |
99 | 15:8 | SPI 4BA read command |
100 | 7:0 | SPI 3BA read command |
104 Flash configuration register 2
107 | Bits | Description |
108 |-------|----------------------------|
109 | 31:24 | QSPI 4BA fast read command |
110 | 23:16 | QSPI 3BA fast read command |
111 | 15:8 | SPI 4BA fast read command |
112 | 7:0 | SPI 3BA fast read command |
116 Flash configuration register 3
119 | Bits | Description |
120 |-------|--------------------------|
121 | 31:24 | QSPI 4BA program command |
122 | 23:16 | QSPI 3BA program command |
123 | 15:8 | SPI 4BA program command |
124 | 7:0 | SPI 3BA program command |
128 Flash configuration register 4
131 Cycles to keep CS asserted after operation completion. Used to support high-throughput multi-cycle transfers with specific Flash devices.
133 See also "Flash configuration register 5"
137 Flash configuration register 5
140 | Bits | Description |
141 |------|-------------------------|
143 | 1 | Allow multicycle writes |
144 | 0 | Allow multicycle reads |
148 Core control register 1
151 | Bits | Description | |
152 |------|-------------|--------------------------|
153 | | 31:1 | Reserved |
154 | | 0 | User command mode enable |
156 User command mode operates in conjunction with "Core data register 1" to support custom (non-data-I/O) SPI commands.
162 Data transfer to/from SPI device in user command mode
164 See also "Core control register 1"
168 Tercel is licensed under the terms of the GNU LGPLv3. See LICENSE.tercel for details.
170 # DOCUMENTATION CREDITS
172 (c) 2022 Raptor Engineering, LLC