aquila/lpc_slave.v

   1 // © 2017 - 2022 Raptor Engineering, LLC
   2 //
   3 // Released under the terms of the LGPL v3+
   4 // See the LICENSE file for full details
   5
   6 module lpc_slave_interface(
   7                 output wire [27:0] address,
   8                 input wire [7:0] tx_data,
   9                 output reg [7:0] rx_data,
  10                 output reg tpm_cycle,
  11                 output reg firmware_cycle,
  12                 input wire continue,
  13                 input wire data_ack,
  14                 input wire transfer_error,
  15                 input wire exception_ack,
  16                 output reg address_ready,
  17                 output reg data_ready,
  18                 output reg data_ready_cont,
  19                 output reg continue_cont,
  20                 output reg [2:0] exception,
  21                 output wire data_direction,     // 0 == read from slave, 1 == write to slave
  22                 input wire [16:0] irq_request,
  23                 input wire irq_tx_ready,
  24                 output reg irq_tx_queued,
  25
  26                 input wire [8:0] lpc_fw_input_xfer_write_addr,
  27                 input wire [7:0] lpc_fw_input_xfer_write_data,
  28                 input wire lpc_fw_input_xfer_write_clk,
  29                 input wire lpc_fw_input_xfer_write_wren,
  30                 input wire [8:0] lpc_fw_output_xfer_read_addr,
  31                 output wire [7:0] lpc_fw_output_xfer_read_data,
  32                 input wire lpc_fw_output_xfer_read_clk,
  33
  34                 input wire [8:0] ipmi_bt_input_xfer_write_addr,
  35                 input wire [7:0] ipmi_bt_input_xfer_write_data,
  36                 input wire ipmi_bt_input_xfer_write_clk,
  37                 input wire ipmi_bt_input_xfer_write_wren,
  38                 input wire [8:0] ipmi_bt_output_xfer_read_addr,
  39                 output wire [7:0] ipmi_bt_output_xfer_read_data,
  40                 input wire ipmi_bt_output_xfer_read_clk,
  41
  42                 input wire [15:0] range1_start,
  43                 input wire [15:0] range1_end,
  44                 input wire [15:0] range2_start,
  45                 input wire [15:0] range2_end,
  46                 input wire [15:0] range3_start,
  47                 input wire [15:0] range3_end,
  48                 input wire [15:0] range4_start,
  49                 input wire [15:0] range4_end,
  50                 input wire [15:0] range5_start,
  51                 input wire [15:0] range5_end,
  52                 input wire [15:0] range6_start,
  53                 input wire [15:0] range6_end,
  54
  55                 input wire enable_vuart1,
  56                 output wire [31:0] vuart1_status_register,
  57                 input wire [31:0] vuart1_control_register,
  58                 output wire vuart1_assert_b2h_break_clear,
  59                 output wire vuart1_tx_fifo_reset,
  60                 output wire vuart1_tx_fifo_wren,
  61                 output wire [7:0] vuart1_tx_fifo_data,
  62                 input wire vuart1_tx_fifo_full,
  63                 input wire vuart1_tx_fifo_almost_full,
  64                 input wire vuart1_tx_fifo_empty,
  65
  66                 output wire vuart1_rx_fifo_reset,
  67                 output wire vuart1_rx_fifo_rpop,
  68                 input wire [7:0] vuart1_rx_fifo_data,
  69                 input wire vuart1_rx_fifo_empty,
  70                 input wire vuart1_rx_fifo_almost_empty,
  71                 input wire vuart1_rx_fifo_full,
  72                 input wire [3:0] vuart1_rx_data_available_count,
  73
  74                 input wire enable_vuart2,
  75                 output wire [31:0] vuart2_status_register,
  76                 input wire [31:0] vuart2_control_register,
  77                 output wire vuart2_assert_b2h_break_clear,
  78                 output wire vuart2_tx_fifo_reset,
  79                 output wire vuart2_tx_fifo_wren,
  80                 output wire [7:0] vuart2_tx_fifo_data,
  81                 input wire vuart2_tx_fifo_full,
  82                 input wire vuart2_tx_fifo_almost_full,
  83                 input wire vuart2_tx_fifo_empty,
  84
  85                 output wire vuart2_rx_fifo_reset,
  86                 output wire vuart2_rx_fifo_rpop,
  87                 input wire [7:0] vuart2_rx_fifo_data,
  88                 input wire vuart2_rx_fifo_empty,
  89                 input wire vuart2_rx_fifo_almost_empty,
  90                 input wire vuart2_rx_fifo_full,
  91                 input wire [3:0] vuart2_rx_data_available_count,
  92
  93                 input wire enable_ipmi_bt,
  94                 input wire ipmi_bt_alt_irq,
  95                 input wire [15:0] ipmi_bt_port_base_address,
  96
  97                 output wire ipmi_bt_bmc_to_host_ctl_sms_ack,
  98                 output wire ipmi_bt_bmc_to_host_ctl_attn_ack,
  99                 output wire ipmi_bt_host_to_bmc_ctl_attn_req,
 100                 output wire ipmi_bt_host_to_bmc_ctl_oem0_req,
 101                 output wire ipmi_bt_irq_ack,
 102                 output wire ipmi_bt_irq_bmc_reset,
 103                 output wire ipmi_bt_host_to_bmc_ctl_h_busy,
 104                 output wire ipmi_bt_irq_enable,
 105
 106                 input wire ipmi_bt_bmc_to_host_ctl_sms_req,
 107                 input wire ipmi_bt_bmc_to_host_ctl_attn_req,
 108                 input wire ipmi_bt_bmc_to_host_ctl_sms_ack_cont,
 109                 input wire ipmi_bt_bmc_to_host_ctl_attn_ack_cont,
 110                 input wire ipmi_bt_host_to_bmc_ctl_attn_req_cont,
 111                 input wire ipmi_bt_host_to_bmc_ctl_oem0_req_cont,
 112                 input wire ipmi_bt_irq_ack_cont,
 113                 input wire ipmi_bt_irq_bmc_reset_cont,
 114                 input wire ipmi_bt_bmc_to_host_ctl_b_busy,
 115                 input wire ipmi_bt_irq_req,
 116
 117                 output wire [3:0] fw_idsel,
 118                 output wire [3:0] fw_msize,
 119
 120                 output wire [15:0] debug_port,
 121
 122                 output reg [3:0] lpc_data_out,  // These three signals must have I/O output register enabled in top level SB_IO or equivalent
 123                 input wire [3:0] lpc_data_in,
 124                 output reg lpc_data_direction,  // 0 == tristate (input), 1 == driven (output)
 125                 output reg lpc_irq_out,
 126                 input wire lpc_irq_in,
 127                 output wire lpc_irq_direction,  // 0 == tristate (input), 1 == driven (output)
 128
 129                 input wire lpc_frame_n,
 130                 input wire lpc_reset_n,
 131                 input wire lpc_clock
 132         );
 133
 134         parameter VUART1_BASE_ADDRESS = 16'h03f8;
 135         parameter VUART1_IRQ = 4;
 136         parameter VUART2_BASE_ADDRESS = 16'h02f8;
 137         parameter VUART2_IRQ = 3;
 138
 139         parameter IPMI_BT_IRQ = 10;
 140         parameter IPMI_BT_ALT_IRQ = 11;
 141
 142         parameter LPC_CODEWORD_ISA_START = 4'b0000;
 143         parameter LPC_CODEWORD_FWR_START = 4'b1101;
 144         parameter LPC_CODEWORD_FWW_START = 4'b1110;
 145         parameter LPC_CODEWORD_TPM_START = 4'b0101;
 146
 147         parameter LPC_CODEWORD_SYNC_READY = 4'b0000;
 148         parameter LPC_CODEWORD_SYNC_SWAIT = 4'b0101;
 149         parameter LPC_CODEWORD_SYNC_LWAIT = 4'b0110;
 150         parameter LPC_CODEWORD_SYNC_ERROR = 4'b1010;
 151         parameter LPC_CODEWORD_TURNAROUND = 4'b1111;
 152
 153         parameter LPC_CYCLE_TYPE_IO = 2'b00;
 154
 155         parameter LPC_RX_TRANSFER_STATE_IDLE = 0;
 156         parameter LPC_RX_TRANSFER_STATE_TR01 = 1;
 157         parameter LPC_RX_TRANSFER_STATE_TR02 = 2;
 158         parameter LPC_RX_TRANSFER_STATE_TR03 = 3;
 159         parameter LPC_RX_TRANSFER_STATE_TR04 = 4;
 160         parameter LPC_RX_TRANSFER_STATE_TR05 = 5;
 161         parameter LPC_RX_TRANSFER_STATE_TR06 = 6;
 162         parameter LPC_RX_TRANSFER_STATE_TR07 = 7;
 163         parameter LPC_RX_TRANSFER_STATE_TR08 = 8;
 164         parameter LPC_RX_TRANSFER_STATE_TR09 = 9;
 165
 166         parameter LPC_RX_TRANSFER_STATE_FR01 = 10;
 167         parameter LPC_RX_TRANSFER_STATE_FR02 = 11;
 168         parameter LPC_RX_TRANSFER_STATE_FR03 = 12;
 169         parameter LPC_RX_TRANSFER_STATE_FR04 = 13;
 170         parameter LPC_RX_TRANSFER_STATE_FR05 = 14;
 171         parameter LPC_RX_TRANSFER_STATE_FR06 = 15;
 172         parameter LPC_RX_TRANSFER_STATE_FR07 = 16;
 173         parameter LPC_RX_TRANSFER_STATE_FR08 = 17;
 174         parameter LPC_RX_TRANSFER_STATE_FR09 = 18;
 175         parameter LPC_RX_TRANSFER_STATE_FR10 = 19;
 176
 177         parameter LPC_RX_TRANSFER_STATE_IW01 = 20;
 178
 179         parameter LPC_TX_TRANSFER_STATE_IDLE = 0;
 180         parameter LPC_TX_TRANSFER_STATE_TR01 = 1;
 181         parameter LPC_TX_TRANSFER_STATE_TR02 = 2;
 182         parameter LPC_TX_TRANSFER_STATE_TR03 = 3;
 183         parameter LPC_TX_TRANSFER_STATE_TR04 = 4;
 184         parameter LPC_TX_TRANSFER_STATE_TR05 = 5;
 185         parameter LPC_TX_TRANSFER_STATE_TR06 = 6;
 186         parameter LPC_TX_TRANSFER_STATE_TR07 = 7;
 187         parameter LPC_TX_TRANSFER_STATE_TR08 = 8;
 188         parameter LPC_TX_TRANSFER_STATE_TR09 = 9;
 189         parameter LPC_TX_TRANSFER_STATE_TR10 = 10;
 190         parameter LPC_TX_TRANSFER_STATE_TR11 = 11;
 191
 192         parameter LPC_TX_TRANSFER_STATE_FR01 = 12;
 193         parameter LPC_TX_TRANSFER_STATE_FR02 = 13;
 194         parameter LPC_TX_TRANSFER_STATE_FR03 = 14;
 195         parameter LPC_TX_TRANSFER_STATE_FR04 = 15;
 196         parameter LPC_TX_TRANSFER_STATE_FR05 = 16;
 197
 198         parameter LPC_SERIRQ_STATE_IDLE = 0;
 199         parameter LPC_SERIRQ_STATE_TR01 = 1;
 200         parameter LPC_SERIRQ_STATE_TR02 = 2;
 201         parameter LPC_SERIRQ_STATE_TR03 = 3;
 202         parameter LPC_SERIRQ_STATE_TR04 = 4;
 203
 204         reg [4:0] rx_transfer_state = 0;
 205         reg [4:0] tx_transfer_state = 0;
 206         reg [2:0] serirq_state = 0;
 207         reg start_tx_cycle = 0;
 208         reg abort_tx_cycle = 0;
 209         reg tx_cycle_done = 0;
 210         reg lpc_frame_n_prev = 1;
 211         reg [1:0] cycle_type = 0;
 212         reg cycle_direction;            // 0 == read, 1 == write
 213         reg [27:0] io_address = 0;      // Lower 16 bits I/O cycles only, full 28 bits used for FW cycles
 214
 215         reg [3:0] fw_cycle_idsel = 0;
 216         reg [3:0] fw_cycle_msize = 0;
 217
 218         reg vuart1_cycle = 0;
 219         reg vuart2_cycle = 0;
 220         reg ipmi_bt_cycle = 0;
 221         reg range_select_cycle = 0;
 222
 223         reg [3:0] vuart1_ier = 0;
 224         wire [7:0] vuart1_iir;
 225         reg [7:0] vuart1_lcr = 0;
 226         reg [4:0] vuart1_mcr = 0;
 227         wire [7:0] vuart1_lsr;
 228         reg [7:0] vuart1_msr = 0;
 229         reg [7:0] vuart1_scr = 0;
 230         reg [7:0] vuart1_dll = 0;
 231         reg [7:0] vuart1_dlm = 0;
 232         reg [2:0] vuart1_interrupt_id = 0;
 233         reg vuart1_interrupt_pending = 0;
 234         reg vuart1_iir_read_tx_empty_assert = 0;
 235         reg vuart1_lsr_read_assert = 0;
 236         reg vuart1_rx_break_irq_pending = 0;
 237         reg vuart1_rx_break_request_prev = 0;
 238         reg vuart1_tx_fifo_empty_prev = 0;
 239         reg vuart1_tx_fifo_empty_irq_pending = 0;
 240         reg vuart1_fifos_enabled = 0;
 241         reg [1:0] vuart1_rcvr_trigger = 0;
 242         reg vuart1_assert_b2h_break_clear_reg = 0;
 243         reg [8:0] vuart1_rx_fifo_read_timeout_counter = 0;
 244         reg vuart1_rx_data_queue_contents_read_timeout = 0;
 245         reg vuart1_rx_data_queue_contents_past_trigger = 0;
 246
 247         assign vuart1_iir[7] = vuart1_fifos_enabled;
 248         assign vuart1_iir[6] = vuart1_fifos_enabled;
 249         assign vuart1_iir[5:4] = 0;
 250         assign vuart1_iir[3:1] = vuart1_interrupt_id;
 251         assign vuart1_iir[0] = !vuart1_interrupt_pending;
 252
 253         assign vuart1_lsr[7] = 0;
 254         assign vuart1_lsr[6] = vuart1_tx_fifo_empty;
 255         assign vuart1_lsr[5] = vuart1_tx_fifo_empty;
 256         assign vuart1_lsr[4] = 0;       // BREAK is implemented via an external signal from the BMC, ORed over this bit
 257         assign vuart1_lsr[3] = 0;
 258         assign vuart1_lsr[2] = 0;
 259         assign vuart1_lsr[1] = 0;
 260         assign vuart1_lsr[0] = !vuart1_rx_fifo_empty;
 261
 262         assign vuart1_assert_b2h_break_clear = vuart1_assert_b2h_break_clear_reg;
 263
 264         reg vuart1_tx_fifo_reset_reg = 0;
 265         reg vuart1_tx_fifo_wren_reg = 0;
 266         reg [7:0] vuart1_tx_fifo_data_reg = 0;
 267         reg vuart1_rx_fifo_reset_reg = 0;
 268         reg vuart1_rx_fifo_rpop_reg = 0;
 269
 270         assign vuart1_tx_fifo_reset = vuart1_tx_fifo_reset_reg;
 271         assign vuart1_tx_fifo_wren = vuart1_tx_fifo_wren_reg;
 272         assign vuart1_tx_fifo_data = vuart1_tx_fifo_data_reg;
 273         assign vuart1_rx_fifo_reset = vuart1_rx_fifo_reset_reg;
 274         assign vuart1_rx_fifo_rpop = vuart1_rx_fifo_rpop_reg;
 275
 276         reg [3:0] vuart2_ier = 0;
 277         wire [7:0] vuart2_iir;
 278         reg [7:0] vuart2_lcr = 0;
 279         reg [4:0] vuart2_mcr = 0;
 280         wire [7:0] vuart2_lsr;
 281         reg [7:0] vuart2_msr = 0;
 282         reg [7:0] vuart2_scr = 0;
 283         reg [7:0] vuart2_dll = 0;
 284         reg [7:0] vuart2_dlm = 0;
 285         reg [2:0] vuart2_interrupt_id = 0;
 286         reg vuart2_interrupt_pending = 0;
 287         reg vuart2_iir_read_tx_empty_assert = 0;
 288         reg vuart2_lsr_read_assert = 0;
 289         reg vuart2_rx_break_irq_pending = 0;
 290         reg vuart2_rx_break_request_prev = 0;
 291         reg vuart2_tx_fifo_empty_prev = 0;
 292         reg vuart2_tx_fifo_empty_irq_pending = 0;
 293         reg vuart2_fifos_enabled = 0;
 294         reg [1:0] vuart2_rcvr_trigger = 0;
 295         reg vuart2_assert_b2h_break_clear_reg = 0;
 296         reg [8:0] vuart2_rx_fifo_read_timeout_counter = 0;
 297         reg vuart2_rx_data_queue_contents_read_timeout = 0;
 298         reg vuart2_rx_data_queue_contents_past_trigger = 0;
 299
 300         assign vuart2_iir[7] = vuart2_fifos_enabled;
 301         assign vuart2_iir[6] = vuart2_fifos_enabled;
 302         assign vuart2_iir[5:4] = 0;
 303         assign vuart2_iir[3:1] = vuart2_interrupt_id;
 304         assign vuart2_iir[0] = !vuart2_interrupt_pending;
 305
 306         assign vuart2_lsr[7] = 0;
 307         assign vuart2_lsr[6] = vuart2_tx_fifo_empty;
 308         assign vuart2_lsr[5] = vuart2_tx_fifo_empty;
 309         assign vuart2_lsr[4] = 0;       // BREAK is implemented via an external signal from the BMC, ORed over this bit
 310         assign vuart2_lsr[3] = 0;
 311         assign vuart2_lsr[2] = 0;
 312         assign vuart2_lsr[1] = 0;
 313         assign vuart2_lsr[0] = !vuart2_rx_fifo_empty;
 314
 315         assign vuart2_assert_b2h_break_clear = vuart2_assert_b2h_break_clear_reg;
 316
 317         reg vuart2_tx_fifo_reset_reg = 0;
 318         reg vuart2_tx_fifo_wren_reg = 0;
 319         reg [7:0] vuart2_tx_fifo_data_reg = 0;
 320         reg vuart2_rx_fifo_reset_reg = 0;
 321         reg vuart2_rx_fifo_rpop_reg = 0;
 322
 323         assign vuart2_tx_fifo_reset = vuart2_tx_fifo_reset_reg;
 324         assign vuart2_tx_fifo_wren = vuart2_tx_fifo_wren_reg;
 325         assign vuart2_tx_fifo_data = vuart2_tx_fifo_data_reg;
 326         assign vuart2_rx_fifo_reset = vuart2_rx_fifo_reset_reg;
 327         assign vuart2_rx_fifo_rpop = vuart2_rx_fifo_rpop_reg;
 328
 329         assign vuart1_status_register = {16'h00, vuart1_fifos_enabled, 1'b0, vuart1_rcvr_trigger, vuart1_mcr, vuart1_lcr};
 330         assign vuart2_status_register = {16'h00, vuart2_fifos_enabled, 1'b0, vuart2_rcvr_trigger, vuart2_mcr, vuart2_lcr};
 331
 332         reg [16:0] active_irq_request = 0;
 333         reg [3:0] irq_delay_counter = 0;
 334         reg [4:0] irq_frame_number = 0;
 335         reg lpc_irq_in_prev_1 = 1;
 336         reg lpc_irq_in_prev_2 = 1;
 337         reg lpc_irq_in_prev_3 = 1;
 338         reg irq_tx_ready_prev = 0;
 339         reg irq_quiet_mode = 0;
 340
 341         reg lpc_irq_direction_reg = 0;
 342
 343         reg lpc_slave_write_complete = 0;
 344
 345         assign address = io_address;
 346         assign data_direction = cycle_direction;
 347
 348         assign fw_idsel = fw_cycle_idsel;
 349         assign fw_msize = fw_cycle_msize;
 350
 351 `ifdef LPC_SLAVE_DEBUG
 352         // Debug port
 353         assign debug_port[3:0] = lpc_data_in;
 354         assign debug_port[4] = lpc_frame_n;
 355         assign debug_port[5] = lpc_reset_n;
 356         assign debug_port[6] = cycle_direction;
 357         assign debug_port[7] = lpc_clock;
 358 //      assign debug_port[11:8] = rx_transfer_state[3:0];
 359 //      assign debug_port[9:8] = rx_transfer_state[1:0];
 360 //      assign debug_port[11] = vuart1_cycle;
 361 //      assign debug_port[10] = ipmi_bt_cycle;
 362 //      assign debug_port[15:12] = tx_transfer_state[3:0];
 363 //      assign debug_port[15:8] = lpc_fw_input_xfer_read_data;
 364         assign debug_port[12] = lpc_irq_in;
 365         assign debug_port[11] = lpc_irq_direction;
 366         assign debug_port[10:8] = serirq_state[2:0];
 367 //      assign debug_port[12:11] = irq_delay_counter[1:0];
 368 //      assign debug_port[12] = lpc_irq_out;
 369 //      assign debug_port[14:13] = irq_frame_number[1:0];
 370 //      assign debug_port[14:12] = serirq_state;
 371 //      assign debug_port[15] = irq_quiet_mode;
 372 //      assign debug_port[8] = 0;
 373 //      assign debug_port[9] = firmware_cycle;
 374 //      assign debug_port[10] = data_ready;
 375 //      assign debug_port[11] = address_ready;
 376 //      assign debug_port[15:12] = fw_cycle_msize;
 377 `else
 378         assign debug_port = 16'h0000;
 379 `endif
 380
 381         reg tx_cycle_done_reg_rx = 0;
 382
 383         reg [16:0] irq_request_reg = 0;
 384         reg irq_tx_ready_reg = 0;
 385
 386         reg [8:0] lpc_fw_input_xfer_read_addr;
 387         wire [7:0] lpc_fw_input_xfer_read_data;
 388         reg [8:0] lpc_fw_output_xfer_write_addr;
 389         reg [7:0] lpc_fw_output_xfer_write_data;
 390         reg lpc_fw_output_xfer_write_wren;
 391
 392         reg [8:0] ipmi_bt_input_xfer_read_addr;
 393         wire [7:0] ipmi_bt_input_xfer_read_data;
 394         reg [8:0] ipmi_bt_output_xfer_write_addr;
 395         reg [7:0] ipmi_bt_output_xfer_write_data;
 396         reg ipmi_bt_output_xfer_write_wren;
 397
 398         reg [8:0] fw_cycle_rx_nibble_counter;
 399         reg [7:0] fw_cycle_tx_byte_counter;
 400
 401         reg rx_special_data_ack = 0;
 402         reg rx_special_continue = 0;
 403         reg [7:0] special_tx_data = 0;
 404
 405         reg ipmi_bt_bmc_to_host_ctl_sms_ack_reg = 0;
 406         reg ipmi_bt_bmc_to_host_ctl_attn_ack_reg = 0;
 407         reg ipmi_bt_host_to_bmc_ctl_attn_req_reg = 0;
 408         reg ipmi_bt_host_to_bmc_ctl_oem0_req_reg = 0;
 409         reg ipmi_bt_irq_ack_reg = 0;
 410         reg ipmi_bt_irq_bmc_reset_reg = 0;
 411         reg ipmi_bt_host_to_bmc_ctl_h_busy_reg = 0;
 412         reg ipmi_bt_irq_enable = 0;
 413
 414         assign ipmi_bt_bmc_to_host_ctl_sms_ack = ipmi_bt_bmc_to_host_ctl_sms_ack_reg;
 415         assign ipmi_bt_bmc_to_host_ctl_attn_ack = ipmi_bt_bmc_to_host_ctl_attn_ack_reg;
 416         assign ipmi_bt_host_to_bmc_ctl_attn_req = ipmi_bt_host_to_bmc_ctl_attn_req_reg;
 417         assign ipmi_bt_host_to_bmc_ctl_oem0_req = ipmi_bt_host_to_bmc_ctl_oem0_req_reg;
 418         assign ipmi_bt_irq_ack = ipmi_bt_irq_ack_reg;
 419         assign ipmi_bt_irq_bmc_reset = ipmi_bt_irq_bmc_reset_reg;
 420         assign ipmi_bt_host_to_bmc_ctl_h_busy = ipmi_bt_host_to_bmc_ctl_h_busy_reg;
 421
 422         assign lpc_irq_direction = lpc_irq_direction_reg;
 423
 424         wire [16:0] vuart_irq_request_overlay;
 425         assign vuart_irq_request_overlay = (vuart2_interrupt_pending << VUART2_IRQ) | (vuart1_interrupt_pending << VUART1_IRQ);
 426
 427         wire [16:0] ipmi_bt_irq_request_overlay;
 428         assign ipmi_bt_irq_request_overlay = (ipmi_bt_alt_irq)?(ipmi_bt_irq_req << IPMI_BT_ALT_IRQ):(ipmi_bt_irq_req << IPMI_BT_IRQ);
 429
 430         always @(posedge lpc_clock) begin
 431                 // Avoid logic glitches due to these signals crossing clock domains
 432                 irq_request_reg <= irq_request;
 433                 irq_tx_ready_reg <= irq_tx_ready;
 434
 435                 if (!lpc_reset_n) begin
 436                         irq_quiet_mode <= 0;
 437                         irq_tx_queued <= 0;
 438                         lpc_irq_in_prev_1 <= 1;
 439                         lpc_irq_in_prev_2 <= 1;
 440                         lpc_irq_in_prev_3 <= 1;
 441                         lpc_irq_out <= 1;
 442                         lpc_irq_direction_reg <= 0;
 443                         serirq_state <= LPC_SERIRQ_STATE_IDLE;
 444                 end else begin
 445                         case (serirq_state)
 446                                 LPC_SERIRQ_STATE_IDLE: begin
 447                                         if (irq_quiet_mode && irq_tx_ready_reg && !irq_tx_ready_prev) begin
 448                                                 active_irq_request <= active_irq_request | irq_request_reg | vuart_irq_request_overlay | ipmi_bt_irq_request_overlay;
 449                                                 irq_tx_queued <= 1;
 450                                                 irq_delay_counter <= 0;
 451
 452                                                 // Initiate quiet mode transfer
 453                                                 lpc_irq_out <= 0;
 454                                                 lpc_irq_direction_reg <= 1;
 455                                                 serirq_state <= LPC_SERIRQ_STATE_TR01;
 456                                         end else begin
 457                                                 // Detect potential start signal from host
 458                                                 // This can occur in either quiet or continuous mode
 459                                                 if (!lpc_irq_in) begin
 460                                                         if (irq_delay_counter > 2) begin
 461                                                                 // Latch current IRQ requests
 462                                                                 active_irq_request <= active_irq_request | irq_request_reg | vuart_irq_request_overlay | ipmi_bt_irq_request_overlay;
 463                                                                 serirq_state <= LPC_SERIRQ_STATE_TR02;
 464                                                         end else begin
 465                                                                 irq_delay_counter <= irq_delay_counter + 1;
 466                                                         end
 467                                                 end else begin
 468                                                         irq_delay_counter <= 0;
 469                                                 end
 470                                         end
 471                                 end
 472                                 LPC_SERIRQ_STATE_TR01: begin
 473                                         // Tristate bus
 474                                         lpc_irq_out <= 0;
 475                                         lpc_irq_direction_reg <= 0;
 476                                         serirq_state <= LPC_SERIRQ_STATE_TR02;
 477                                 end
 478                                 LPC_SERIRQ_STATE_TR02: begin
 479                                         // Wait for completion of start signal from host
 480                                         if (lpc_irq_in) begin
 481                                                 // IRQ0 needs to be asserted nearly immediately after the end of the start pulse
 482                                                 // if it is to be asserted at all.  Handle IRQ0 start pulse assertion here, as the
 483                                                 // heavy pipelining of the IRQ transmitter will not allow a short enough delay to
 484                                                 // launch IRQ0 in the next state...
 485                                                 if (active_irq_request[0]) begin
 486                                                         // Drive IRQ assert for IRQ0
 487                                                         lpc_irq_out <= 0;
 488                                                         lpc_irq_direction_reg <= 1;
 489                                                 end
 490                                                 irq_delay_counter <= 1;
 491                                                 irq_frame_number <= 0;
 492                                                 serirq_state <= LPC_SERIRQ_STATE_TR03;
 493                                         end
 494                                 end
 495                                 LPC_SERIRQ_STATE_TR03: begin
 496                                         if (irq_frame_number < 17) begin
 497                                                 if (irq_delay_counter == 0) begin
 498                                                         if (active_irq_request[irq_frame_number]) begin
 499                                                                 // Drive IRQ assert
 500                                                                 lpc_irq_out <= 0;
 501                                                                 lpc_irq_direction_reg <= 1;
 502                                                         end
 503                                                 end else if (irq_delay_counter == 1) begin
 504                                                         if (active_irq_request[irq_frame_number]) begin
 505                                                                 // Drive line back high to prepare for TAR cycle.
 506                                                                 // This avoids the line floating low / undetermined for an extended period of time
 507                                                                 // after we stop driving it; i.e. not relying solely on pullup resistor response.
 508                                                                 lpc_irq_out <= 1;
 509                                                                 lpc_irq_direction_reg <= 1;
 510                                                         end
 511                                                 end else begin
 512                                                         lpc_irq_out <= 1;
 513                                                         lpc_irq_direction_reg <= 0;
 514                                                 end
 515                                         end else begin
 516                                                 lpc_irq_out <= 1;
 517                                                 serirq_state <= LPC_SERIRQ_STATE_TR04;
 518                                         end
 519
 520                                         if (irq_delay_counter > 1) begin
 521                                                 irq_frame_number <= irq_frame_number + 1;
 522                                                 irq_delay_counter <= 0;
 523                                         end else begin
 524                                                 irq_delay_counter <= irq_delay_counter + 1;
 525                                         end
 526                                 end
 527                                 LPC_SERIRQ_STATE_TR04: begin
 528                                         // Wait for rising edge
 529                                         if (!lpc_irq_in_prev_1 && lpc_irq_in) begin
 530                                                 if (!lpc_irq_in_prev_3 && !lpc_irq_in_prev_2 && !lpc_irq_in_prev_1) begin
 531                                                         irq_quiet_mode <= 0;
 532                                                 end else begin
 533                                                         irq_quiet_mode <= 1;
 534                                                 end
 535                                                 active_irq_request <= 0;
 536                                                 serirq_state <= LPC_SERIRQ_STATE_IDLE;
 537                                         end
 538
 539                                         // Ensure bus is tristated
 540                                         lpc_irq_direction_reg <= 0;
 541                                 end
 542                                 default: begin
 543                                         // Should never reach this state
 544                                         serirq_state <= LPC_SERIRQ_STATE_IDLE;
 545                                 end
 546                         endcase
 547                 end
 548
 549                 lpc_irq_in_prev_1 <= lpc_irq_in;
 550                 lpc_irq_in_prev_2 <= lpc_irq_in_prev_1;
 551                 lpc_irq_in_prev_3 <= lpc_irq_in_prev_2;
 552                 irq_tx_ready_prev <= irq_tx_ready_reg;
 553
 554                 if ((serirq_state != LPC_SERIRQ_STATE_IDLE) && !irq_tx_ready_reg) begin
 555                         irq_tx_queued <= 0;
 556                 end
 557         end
 558
 559         always @(posedge lpc_clock) begin
 560                 // Avoid logic glitches due to this signal crossing clock domains
 561                 tx_cycle_done_reg_rx = tx_cycle_done;
 562
 563                 if (!lpc_reset_n) begin
 564                         rx_transfer_state <= LPC_RX_TRANSFER_STATE_IDLE;
 565
 566                         lpc_data_direction <= 0;
 567                         abort_tx_cycle <= 1;
 568
 569                         rx_special_data_ack <= 0;
 570                         rx_special_continue <= 0;
 571
 572                         vuart1_lcr <= 0;
 573                         vuart1_fifos_enabled <= 0;
 574                         vuart1_interrupt_pending <= 0;
 575                         vuart1_iir_read_tx_empty_assert <= 0;
 576                         vuart1_tx_fifo_empty_irq_pending <= 0;
 577                         vuart1_lsr_read_assert <= 0;
 578                         vuart1_rx_break_irq_pending <= 0;
 579                         vuart1_rx_break_request_prev <= 0;
 580                         vuart1_interrupt_id <= 0;
 581                         vuart1_rcvr_trigger <= 0;
 582                         vuart1_tx_fifo_reset_reg <= 0;
 583                         vuart1_rx_fifo_reset_reg <= 0;
 584                         vuart1_rx_fifo_rpop_reg <= 0;
 585                         vuart1_rx_data_queue_contents_read_timeout <= 0;
 586                         vuart1_rx_data_queue_contents_past_trigger <= 0;
 587                         vuart2_lcr <= 0;
 588                         vuart2_fifos_enabled <= 0;
 589                         vuart2_interrupt_pending <= 0;
 590                         vuart2_iir_read_tx_empty_assert <= 0;
 591                         vuart2_tx_fifo_empty_irq_pending <= 0;
 592                         vuart2_lsr_read_assert <= 0;
 593                         vuart2_rx_break_irq_pending <= 0;
 594                         vuart2_rx_break_request_prev <= 0;
 595                         vuart2_interrupt_id <= 0;
 596                         vuart2_rcvr_trigger <= 0;
 597                         vuart2_tx_fifo_reset_reg <= 0;
 598                         vuart2_rx_fifo_reset_reg <= 0;
 599                         vuart2_rx_fifo_rpop_reg <= 0;
 600                         vuart2_rx_data_queue_contents_read_timeout <= 0;
 601                         vuart2_rx_data_queue_contents_past_trigger <= 0;
 602
 603                         ipmi_bt_bmc_to_host_ctl_sms_ack_reg <= 0;
 604                         ipmi_bt_bmc_to_host_ctl_attn_ack_reg <= 0;
 605                         ipmi_bt_host_to_bmc_ctl_attn_req_reg <= 0;
 606                         ipmi_bt_host_to_bmc_ctl_oem0_req_reg <= 0;
 607                         ipmi_bt_irq_ack_reg <= 0;
 608                         ipmi_bt_irq_bmc_reset_reg <= 0;
 609                         ipmi_bt_host_to_bmc_ctl_h_busy_reg <= 0;
 610                         ipmi_bt_irq_enable <= 0;
 611
 612                         // Signal exception to CPU
 613                         if (!exception_ack) begin
 614                                 exception[1] <= 1;
 615                         end
 616                 end else begin
 617                         if (!lpc_frame_n) begin
 618                                 if ((rx_transfer_state == LPC_RX_TRANSFER_STATE_IDLE)
 619                                         || (rx_transfer_state == LPC_RX_TRANSFER_STATE_TR01)) begin
 620                                         cycle_type <= 0;
 621                                         io_address <= 0;
 622                                         data_ready <= 0;
 623                                         address_ready <= 0;
 624
 625                                         vuart1_cycle <= 0;
 626                                         vuart2_cycle <= 0;
 627                                         ipmi_bt_cycle <= 0;
 628                                         range_select_cycle <= 0;
 629
 630                                         abort_tx_cycle <= 1;
 631                                         if (lpc_data_in == LPC_CODEWORD_ISA_START) begin
 632                                                 cycle_direction <= 0;
 633                                                 tpm_cycle <= 0;
 634                                                 firmware_cycle <= 0;
 635                                                 rx_transfer_state <= LPC_RX_TRANSFER_STATE_TR01;
 636                                         end else begin
 637                                                 if (lpc_data_in == LPC_CODEWORD_TPM_START) begin
 638                                                         cycle_direction <= 0;
 639                                                         tpm_cycle <= 1;
 640                                                         firmware_cycle <= 0;
 641                                                         rx_transfer_state <= LPC_RX_TRANSFER_STATE_TR01;
 642                                                 end else begin
 643                                                         if ((lpc_data_in == LPC_CODEWORD_FWR_START) || (lpc_data_in == LPC_CODEWORD_FWW_START)) begin
 644 `ifdef ENABLE_FIRMWARE_MEMORY_CYCLES
 645                                                                 tpm_cycle <= 0;
 646                                                                 firmware_cycle <= 1;
 647                                                                 if (lpc_data_in == LPC_CODEWORD_FWW_START) begin
 648                                                                         cycle_direction <= 1;
 649                                                                 end else begin
 650                                                                         cycle_direction <= 0;
 651                                                                 end
 652                                                                 rx_transfer_state <= LPC_RX_TRANSFER_STATE_FR01;
 653 `else
 654                                                                 cycle_direction <= 0;
 655                                                                 tpm_cycle <= 0;
 656                                                                 firmware_cycle <= 0;
 657                                                                 rx_transfer_state <= LPC_RX_TRANSFER_STATE_IDLE;
 658 `endif
 659                                                         end else begin
 660                                                                 rx_transfer_state <= LPC_RX_TRANSFER_STATE_IDLE;
 661                                                         end
 662                                                 end
 663                                         end
 664                                 end else begin
 665                                         if (!lpc_frame_n_prev) begin
 666                                                 // Host requested active cycle abort
 667                                                 lpc_data_direction <= 0;
 668                                                 abort_tx_cycle <= 1;
 669                                                 rx_transfer_state <= LPC_RX_TRANSFER_STATE_IDLE;
 670
 671                                                 // Signal exception to CPU
 672                                                 if (!exception_ack) begin
 673                                                         exception[0] <= 1;
 674                                                 end
 675                                         end
 676                                 end
 677                         end else begin
 678                                 case (rx_transfer_state)
 679                                         LPC_RX_TRANSFER_STATE_IDLE: begin
 680                                                 // Idle state
 681                                                 cycle_type <= 0;
 682                                                 cycle_direction <= 0;
 683                                                 io_address <= 0;
 684                                                 tpm_cycle <= 0;
 685                                                 firmware_cycle <= 0;
 686                                                 data_ready <= 0;
 687                                                 address_ready <= 0;
 688
 689                                                 vuart1_cycle <= 0;
 690                                                 vuart2_cycle <= 0;
 691                                                 ipmi_bt_cycle <= 0;
 692                                                 range_select_cycle <= 0;
 693
 694                                                 rx_transfer_state <= LPC_RX_TRANSFER_STATE_IDLE;
 695
 696                                                 abort_tx_cycle <= 1;
 697                                                 lpc_data_direction <= 0;
 698                                         end
 699                                         LPC_RX_TRANSFER_STATE_TR01: begin
 700                                                 // Receive cycle type and direction
 701                                                 cycle_type <= lpc_data_in[3:2];
 702                                                 cycle_direction <= lpc_data_in[1];
 703
 704                                                 rx_transfer_state <= LPC_RX_TRANSFER_STATE_TR02;
 705                                         end
 706                                         LPC_RX_TRANSFER_STATE_TR02: begin
 707                                                 if (cycle_type == LPC_CYCLE_TYPE_IO) begin
 708                                                         // Receive I/O address -- nibble 1
 709                                                         io_address[15:12] <= lpc_data_in;
 710                                                         rx_transfer_state <= LPC_RX_TRANSFER_STATE_TR03;
 711                                                 end else begin
 712                                                         // Cycle type not handled by this peripheral, return to idle
 713                                                         rx_transfer_state <= LPC_RX_TRANSFER_STATE_IDLE;
 714                                                 end
 715
 716                                                 abort_tx_cycle <= 0;
 717                                         end
 718                                         LPC_RX_TRANSFER_STATE_TR03: begin
 719                                                 // Receive I/O address -- nibble 2
 720                                                 io_address[11:8] <= lpc_data_in;
 721                                                 rx_transfer_state <= LPC_RX_TRANSFER_STATE_TR04;
 722                                         end
 723                                         LPC_RX_TRANSFER_STATE_TR04: begin
 724                                                 // Receive I/O address -- nibble 3
 725                                                 io_address[7:4] <= lpc_data_in;
 726                                                 rx_transfer_state <= LPC_RX_TRANSFER_STATE_TR05;
 727                                         end
 728                                         LPC_RX_TRANSFER_STATE_TR05: begin
 729                                                 // Receive I/O address -- nibble 4
 730                                                 io_address[3:0] <= lpc_data_in;
 731
 732                                                 // Preliminary target peripheral routing
 733                                                 if (enable_vuart1 && ({io_address[15:4], lpc_data_in[3], 3'b000} == VUART1_BASE_ADDRESS)) begin
 734                                                         vuart1_cycle <= 1;
 735
 736                                                         if (cycle_direction == 0) begin
 737                                                                 // Start driving LAD lines
 738                                                                 lpc_data_direction <= 1;
 739                                                         end
 740                                                 end
 741                                                 if (enable_vuart2 && ({io_address[15:4], lpc_data_in[3], 3'b000} == VUART2_BASE_ADDRESS)) begin
 742                                                         vuart2_cycle <= 1;
 743
 744                                                         if (cycle_direction == 0) begin
 745                                                                 // Start driving LAD lines
 746                                                                 lpc_data_direction <= 1;
 747                                                         end
 748                                                 end
 749                                                 if (enable_ipmi_bt && ({io_address[15:4], lpc_data_in[3:2], 2'b00} == ipmi_bt_port_base_address)) begin
 750                                                         ipmi_bt_cycle <= 1;
 751
 752                                                         if (cycle_direction == 0) begin
 753                                                                 // Start driving LAD lines
 754                                                                 lpc_data_direction <= 1;
 755                                                         end
 756                                                 end
 757                                                 if ((({io_address[15:4], lpc_data_in[3:0]} >= range1_start) && ({io_address[15:4], lpc_data_in[3:0]} <= range1_end))
 758                                                         || (({io_address[15:4], lpc_data_in[3:0]} >= range2_start) && ({io_address[15:4], lpc_data_in[3:0]} <= range2_end))
 759                                                         || (({io_address[15:4], lpc_data_in[3:0]} >= range3_start) && ({io_address[15:4], lpc_data_in[3:0]} <= range3_end))
 760                                                         || (({io_address[15:4], lpc_data_in[3:0]} >= range4_start) && ({io_address[15:4], lpc_data_in[3:0]} <= range4_end))
 761                                                         || (({io_address[15:4], lpc_data_in[3:0]} >= range5_start) && ({io_address[15:4], lpc_data_in[3:0]} <= range5_end))
 762                                                         || (({io_address[15:4], lpc_data_in[3:0]} >= range6_start) && ({io_address[15:4], lpc_data_in[3:0]} <= range6_end))
 763                                                         ) begin
 764                                                         range_select_cycle <= 1;
 765
 766                                                         if (cycle_direction == 0) begin
 767                                                                 // Start driving LAD lines
 768                                                                 lpc_data_direction <= 1;
 769                                                         end
 770                                                 end
 771
 772                                                 rx_transfer_state <= LPC_RX_TRANSFER_STATE_TR06;
 773                                         end
 774                                         LPC_RX_TRANSFER_STATE_TR06: begin
 775                                                 if (vuart1_cycle || vuart2_cycle
 776                                                         || ipmi_bt_cycle || range_select_cycle
 777                                                         || tpm_cycle) begin                                                     // TPM cycles are always decoded
 778                                                         // Address handled by this peripheral
 779                                                         if (cycle_direction == 1) begin
 780                                                                 // Receive I/O data -- nibble 1
 781                                                                 rx_data[3:0] <= lpc_data_in;
 782                                                                 if (!vuart1_cycle && !vuart2_cycle && !ipmi_bt_cycle) begin
 783                                                                         address_ready <= 1;
 784                                                                 end
 785                                                                 rx_transfer_state <= LPC_RX_TRANSFER_STATE_TR07;
 786                                                         end else begin
 787                                                                 if (vuart1_cycle) begin
 788                                                                         case (io_address[2:0])
 789                                                                                 0: begin
 790                                                                                         if (vuart1_lcr[7]) begin
 791                                                                                                 special_tx_data <= vuart1_dll;
 792                                                                                         end else begin
 793                                                                                                 if (!vuart1_rx_fifo_empty) begin
 794                                                                                                         special_tx_data <= vuart1_rx_fifo_data;
 795                                                                                                         vuart1_rx_fifo_rpop_reg <= 1;
 796                                                                                                 end else begin
 797                                                                                                         special_tx_data <= 8'hff;
 798                                                                                                 end
 799                                                                                         end
 800                                                                                 end
 801                                                                                 1: begin
 802                                                                                         if (vuart1_lcr[7]) begin
 803                                                                                                 special_tx_data <= vuart1_dlm;
 804                                                                                         end else begin
 805                                                                                                 special_tx_data <= {4'b0000, vuart1_ier};
 806                                                                                         end
 807                                                                                 end
 808                                                                                 2: begin
 809                                                                                         if (vuart1_interrupt_pending && (vuart1_interrupt_id == 3'b001)) begin
 810                                                                                                 vuart1_iir_read_tx_empty_assert <= 1;
 811                                                                                         end
 812                                                                                         special_tx_data <= vuart1_iir;
 813                                                                                 end
 814                                                                                 3: special_tx_data <= vuart1_lcr;
 815                                                                                 4: special_tx_data <= {3'b111, vuart1_mcr};
 816                                                                                 5: begin
 817                                                                                         if (vuart1_control_register[0]) begin
 818                                                                                                 vuart1_assert_b2h_break_clear_reg <= 1;
 819                                                                                                 special_tx_data <= vuart1_lsr | 8'b00010000;
 820                                                                                         end else begin
 821                                                                                                 special_tx_data <= vuart1_lsr;
 822                                                                                         end
 823                                                                                         vuart1_lsr_read_assert <= 1;
 824                                                                                 end
 825                                                                                 6: special_tx_data <= vuart1_msr;
 826                                                                                 7: special_tx_data <= vuart1_scr;
 827                                                                         endcase
 828
 829                                                                         rx_special_continue <= 1;
 830                                                                 end else if (vuart2_cycle) begin
 831                                                                         case (io_address[2:0])
 832                                                                                 0: begin
 833                                                                                         if (vuart2_lcr[7]) begin
 834                                                                                                 special_tx_data <= vuart2_dll;
 835                                                                                         end else begin
 836                                                                                                 if (!vuart2_rx_fifo_empty) begin
 837                                                                                                         special_tx_data <= vuart2_rx_fifo_data;
 838                                                                                                         vuart2_rx_fifo_rpop_reg <= 1;
 839                                                                                                 end else begin
 840                                                                                                         special_tx_data <= 8'hff;
 841                                                                                                 end
 842                                                                                         end
 843                                                                                 end
 844                                                                                 1: begin
 845                                                                                         if (vuart2_lcr[7]) begin
 846                                                                                                 special_tx_data <= vuart2_dlm;
 847                                                                                         end else begin
 848                                                                                                 special_tx_data <= {4'b0000, vuart2_ier};
 849                                                                                         end
 850                                                                                 end
 851                                                                                 2: begin
 852                                                                                         if (vuart2_interrupt_pending && (vuart2_interrupt_id == 3'b001)) begin
 853                                                                                                 vuart2_iir_read_tx_empty_assert <= 1;
 854                                                                                         end
 855                                                                                         special_tx_data <= vuart2_iir;
 856                                                                                 end
 857                                                                                 3: special_tx_data <= vuart2_lcr;
 858                                                                                 4: special_tx_data <= {3'b111, vuart2_mcr};
 859                                                                                 5: begin
 860                                                                                         if (vuart2_control_register[0]) begin
 861                                                                                                 vuart2_assert_b2h_break_clear_reg <= 1;
 862                                                                                                 special_tx_data <= vuart2_lsr | 8'b00010000;
 863                                                                                         end else begin
 864                                                                                                 special_tx_data <= vuart2_lsr;
 865                                                                                         end
 866                                                                                         vuart2_lsr_read_assert <= 1;
 867                                                                                 end
 868                                                                                 6: special_tx_data <= vuart2_msr;
 869                                                                                 7: special_tx_data <= vuart2_scr;
 870                                                                         endcase
 871
 872                                                                         rx_special_continue <= 1;
 873                                                                 end else if (ipmi_bt_cycle) begin
 874                                                                         case (io_address[1:0])
 875                                                                                 0: begin
 876                                                                                         special_tx_data[7] <= ipmi_bt_bmc_to_host_ctl_b_busy;
 877                                                                                         special_tx_data[6] <= ipmi_bt_host_to_bmc_ctl_h_busy_reg;
 878                                                                                         special_tx_data[5] <= ipmi_bt_host_to_bmc_ctl_oem0_req_reg;
 879                                                                                         special_tx_data[4] <= ipmi_bt_bmc_to_host_ctl_sms_req;
 880                                                                                         special_tx_data[3] <= ipmi_bt_bmc_to_host_ctl_attn_req;
 881                                                                                         special_tx_data[2] <= ipmi_bt_host_to_bmc_ctl_attn_req_reg;
 882                                                                                         special_tx_data[1] <= 1'b0;
 883                                                                                         special_tx_data[0] <= 1'b0;
 884                                                                                 end
 885                                                                                 1: begin
 886                                                                                         special_tx_data <= ipmi_bt_input_xfer_read_data;
 887                                                                                         ipmi_bt_input_xfer_read_addr <= ipmi_bt_input_xfer_read_addr + 1;
 888                                                                                 end
 889                                                                                 2: begin
 890                                                                                         special_tx_data[7:2] = 6'b000000;
 891                                                                                         special_tx_data[1] = ipmi_bt_irq_req;
 892                                                                                         special_tx_data[0] = ipmi_bt_irq_enable;
 893                                                                                 end
 894                                                                         endcase
 895
 896                                                                         rx_special_continue <= 1;
 897                                                                 end else begin
 898                                                                         // Signal CPU that address is ready
 899                                                                         address_ready <= 1;
 900                                                                 end
 901
 902                                                                 // Assert TX cycle start flag for > 1 clock
 903                                                                 start_tx_cycle <= 1;
 904                                                                 rx_transfer_state <= LPC_RX_TRANSFER_STATE_TR09;
 905                                                         end
 906                                                 end else begin
 907                                                         // Address not handled by this peripheral, return to idle
 908                                                         rx_transfer_state <= LPC_RX_TRANSFER_STATE_IDLE;
 909
 910                                                         abort_tx_cycle <= 1;
 911                                                         lpc_data_direction <= 0;
 912                                                 end
 913
 914                                         end
 915                                         LPC_RX_TRANSFER_STATE_TR07: begin
 916                                                 // Receive I/O data -- nibble 2
 917                                                 rx_data[7:4] <= lpc_data_in;
 918                                                 rx_transfer_state <= LPC_RX_TRANSFER_STATE_TR08;
 919
 920                                                 // Start driving LAD lines
 921                                                 lpc_data_direction <= 1;
 922
 923                                                 // Assert TX cycle start flag for > 1 clock
 924                                                 start_tx_cycle <= 1;
 925                                         end
 926                                         LPC_RX_TRANSFER_STATE_TR08: begin
 927                                                 if (vuart1_cycle) begin
 928                                                         case (io_address[2:0])
 929                                                                 0: begin
 930                                                                         if (vuart1_lcr[7]) begin
 931                                                                                 vuart1_dll <= rx_data;
 932                                                                         end else begin
 933                                                                                 if (!vuart1_tx_fifo_full) begin
 934                                                                                         vuart1_tx_fifo_data_reg <= rx_data;
 935                                                                                         vuart1_tx_fifo_wren_reg <= 1;
 936                                                                                 end
 937                                                                         end
 938                                                                 end
 939                                                                 1: begin
 940                                                                         if (vuart1_lcr[7]) begin
 941                                                                                 vuart1_dlm <= rx_data;
 942                                                                         end else begin
 943                                                                                 vuart1_ier <= rx_data[3:0];
 944                                                                         end
 945                                                                 end
 946                                                                 2: begin
 947                                                                         // FIFO control
 948                                                                         vuart1_fifos_enabled <= rx_data[0];
 949                                                                         if (rx_data[1]) begin
 950                                                                                 vuart1_rx_fifo_reset_reg <= 1;
 951                                                                         end
 952                                                                         if (rx_data[2]) begin
 953                                                                                 vuart1_tx_fifo_reset_reg <= 1;
 954                                                                         end
 955                                                                         vuart1_rcvr_trigger <= rx_data[7:6];
 956                                                                 end
 957                                                                 3: vuart1_lcr <= rx_data;
 958                                                                 4: vuart1_mcr <= rx_data[4:0];
 959                                                                 6: vuart1_msr <= rx_data;
 960                                                                 7: vuart1_scr <= rx_data;
 961                                                         endcase
 962                                                         rx_special_data_ack <= 1;
 963
 964                                                         rx_transfer_state <= LPC_RX_TRANSFER_STATE_TR09;
 965                                                 end else if (vuart2_cycle) begin
 966                                                         case (io_address[2:0])
 967                                                                 0: begin
 968                                                                         if (vuart2_lcr[7]) begin
 969                                                                                 vuart2_dll <= rx_data;
 970                                                                         end else begin
 971                                                                                 if (!vuart2_tx_fifo_full) begin
 972                                                                                         vuart2_tx_fifo_data_reg <= rx_data;
 973                                                                                         vuart2_tx_fifo_wren_reg <= 1;
 974                                                                                 end
 975                                                                         end
 976                                                                 end
 977                                                                 1: begin
 978                                                                         if (vuart2_lcr[7]) begin
 979                                                                                 vuart2_dlm <= rx_data;
 980                                                                         end else begin
 981                                                                                 vuart2_ier <= rx_data[3:0];
 982                                                                         end
 983                                                                 end
 984                                                                 2: begin
 985                                                                         // FIFO control
 986                                                                         vuart2_fifos_enabled <= rx_data[0];
 987                                                                         if (rx_data[1]) begin
 988                                                                                 vuart2_rx_fifo_reset_reg <= 1;
 989                                                                         end
 990                                                                         if (rx_data[2]) begin
 991                                                                                 vuart2_tx_fifo_reset_reg <= 1;
 992                                                                         end
 993                                                                         vuart2_rcvr_trigger <= rx_data[7:6];
 994                                                                 end
 995                                                                 3: vuart2_lcr <= rx_data;
 996                                                                 4: vuart2_mcr <= rx_data[4:0];
 997                                                                 6: vuart2_msr <= rx_data;
 998                                                                 7: vuart2_scr <= rx_data;
 999                                                         endcase
1000                                                         rx_special_data_ack <= 1;
1001
1002                                                         rx_transfer_state <= LPC_RX_TRANSFER_STATE_TR09;
1003                                                 end else if (ipmi_bt_cycle) begin
1004                                                         case (io_address[1:0])
1005                                                                 0: begin
1006                                                                         if (rx_data[6]) begin
1007                                                                                 if (ipmi_bt_host_to_bmc_ctl_h_busy_reg) begin
1008                                                                                         ipmi_bt_host_to_bmc_ctl_h_busy_reg <= 1'b0;
1009                                                                                 end else begin
1010                                                                                         ipmi_bt_host_to_bmc_ctl_h_busy_reg <= 1'b1;
1011                                                                                 end
1012                                                                         end
1013                                                                         if (rx_data[5]) begin
1014                                                                                 ipmi_bt_host_to_bmc_ctl_oem0_req_reg <= 1'b1;
1015                                                                         end
1016                                                                         if (rx_data[4]) begin
1017                                                                                 ipmi_bt_bmc_to_host_ctl_sms_ack_reg <= 1'b1;
1018                                                                         end
1019                                                                         if (rx_data[3]) begin
1020                                                                                 ipmi_bt_bmc_to_host_ctl_attn_ack_reg <= 1'b1;
1021                                                                         end
1022                                                                         if (rx_data[2]) begin
1023                                                                                 ipmi_bt_host_to_bmc_ctl_attn_req_reg <= 1'b1;
1024                                                                         end
1025                                                                         if (rx_data[1]) begin
1026                                                                                 ipmi_bt_input_xfer_read_addr <= 0;
1027                                                                         end
1028                                                                         if (rx_data[0]) begin
1029                                                                                 ipmi_bt_output_xfer_write_addr <= 0;
1030                                                                                 ipmi_bt_output_xfer_write_wren <= 0;
1031                                                                         end
1032                                                                 end
1033                                                                 1: begin
1034                                                                         ipmi_bt_output_xfer_write_data <= rx_data;
1035                                                                         ipmi_bt_output_xfer_write_wren <= 1;
1036                                                                 end
1037                                                                 2: begin
1038                                                                         if (rx_data[7]) begin
1039                                                                                 ipmi_bt_irq_bmc_reset_reg <= 1'b1;
1040                                                                         end
1041                                                                         if (rx_data[1]) begin
1042                                                                                 ipmi_bt_irq_ack_reg <= 1'b1;
1043                                                                         end
1044                                                                         ipmi_bt_irq_enable <= rx_data[0];
1045                                                                 end
1046                                                         endcase
1047
1048                                                         lpc_slave_write_complete <= 0;
1049                                                         rx_transfer_state <= LPC_RX_TRANSFER_STATE_IW01;
1050                                                 end else begin
1051                                                         // Signal CPU that address / data are ready
1052                                                         address_ready <= 1;
1053                                                         if (cycle_direction == 1) begin
1054                                                                 data_ready <= 1;
1055                                                         end
1056
1057                                                         rx_transfer_state <= LPC_RX_TRANSFER_STATE_TR09;
1058                                                 end
1059                                         end
1060                                         LPC_RX_TRANSFER_STATE_IW01: begin
1061                                                 if (!lpc_slave_write_complete) begin
1062                                                         if (ipmi_bt_cycle) begin
1063                                                                 case (io_address[1:0])
1064                                                                         1: begin
1065                                                                                 ipmi_bt_output_xfer_write_addr <= ipmi_bt_output_xfer_write_addr + 1;
1066                                                                                 ipmi_bt_output_xfer_write_wren <= 0;
1067                                                                                 lpc_slave_write_complete <= 1;
1068                                                                         end
1069                                                                         2: begin
1070                                                                                 // Handle synchronous IPMI BT IRQ reset handshake signals
1071                                                                                 if (ipmi_bt_irq_bmc_reset_cont) begin
1072                                                                                         ipmi_bt_irq_bmc_reset_reg <= 0;
1073                                                                                 end
1074
1075                                                                                 // Do not continue write until slave has completed its reset cycle
1076                                                                                 if (!ipmi_bt_irq_bmc_reset_reg) begin
1077                                                                                         lpc_slave_write_complete <= 1;
1078                                                                                 end
1079                                                                         end
1080                                                                         default: begin
1081                                                                                 lpc_slave_write_complete <= 1;
1082                                                                         end
1083                                                                 endcase
1084                                                         end else begin
1085                                                                 lpc_slave_write_complete <= 1;
1086                                                         end
1087                                                 end else begin
1088                                                         rx_special_data_ack <= 1;
1089                                                         rx_transfer_state <= LPC_RX_TRANSFER_STATE_TR09;
1090                                                 end
1091                                         end
1092                                         LPC_RX_TRANSFER_STATE_TR09: begin
1093                                                 // Clear special cycle flags if set
1094                                                 if (data_ready_cont) begin
1095                                                         rx_special_data_ack <= 0;
1096                                                 end
1097                                                 if (continue_cont) begin
1098                                                         rx_special_continue <= 0;
1099                                                 end
1100
1101                                                 // Reset VUART FIFO control signals
1102                                                 vuart1_tx_fifo_wren_reg <= 0;
1103                                                 vuart1_tx_fifo_reset_reg <= 0;
1104                                                 vuart1_rx_fifo_rpop_reg <= 0;
1105                                                 vuart1_rx_fifo_reset_reg <= 0;
1106                                                 vuart2_tx_fifo_wren_reg <= 0;
1107                                                 vuart2_tx_fifo_reset_reg <= 0;
1108                                                 vuart2_rx_fifo_rpop_reg <= 0;
1109                                                 vuart2_rx_fifo_reset_reg <= 0;
1110
1111                                                 // Wait for TX cycle to complete
1112                                                 start_tx_cycle <= 0;
1113                                                 if (tx_cycle_done_reg_rx) begin
1114                                                         lpc_data_direction <= 0;
1115                                                         rx_transfer_state <= LPC_RX_TRANSFER_STATE_IDLE;
1116                                                 end
1117                                         end
1118                                         LPC_RX_TRANSFER_STATE_FR01: begin
1119                                                 // Receive IDSEL field
1120                                                 fw_cycle_idsel <= lpc_data_in;
1121                                                 rx_transfer_state <= LPC_RX_TRANSFER_STATE_FR02;
1122                                         end
1123                                         LPC_RX_TRANSFER_STATE_FR02: begin
1124                                                 // Receive firmware cycle address -- nibble 1
1125                                                 io_address[27:24] <= lpc_data_in;
1126                                                 rx_transfer_state <= LPC_RX_TRANSFER_STATE_FR03;
1127
1128                                                 abort_tx_cycle <= 0;
1129                                         end
1130                                         LPC_RX_TRANSFER_STATE_FR03: begin
1131                                                 // Receive firmware cycle address -- nibble 2
1132                                                 io_address[23:20] <= lpc_data_in;
1133                                                 rx_transfer_state <= LPC_RX_TRANSFER_STATE_FR04;
1134                                         end
1135                                         LPC_RX_TRANSFER_STATE_FR04: begin
1136                                                 // Receive firmware cycle address -- nibble 3
1137                                                 io_address[19:16] <= lpc_data_in;
1138                                                 rx_transfer_state <= LPC_RX_TRANSFER_STATE_FR05;
1139                                         end
1140                                         LPC_RX_TRANSFER_STATE_FR05: begin
1141                                                 // Receive firmware cycle address -- nibble 4
1142                                                 io_address[15:12] <= lpc_data_in;
1143                                                 rx_transfer_state <= LPC_RX_TRANSFER_STATE_FR06;
1144                                         end
1145                                         LPC_RX_TRANSFER_STATE_FR06: begin
1146                                                 // Receive firmware cycle address -- nibble 5
1147                                                 io_address[11:8] <= lpc_data_in;
1148                                                 rx_transfer_state <= LPC_RX_TRANSFER_STATE_FR07;
1149                                         end
1150                                         LPC_RX_TRANSFER_STATE_FR07: begin
1151                                                 // Receive firmware cycle address -- nibble 6
1152                                                 io_address[7:4] <= lpc_data_in;
1153                                                 rx_transfer_state <= LPC_RX_TRANSFER_STATE_FR08;
1154                                         end
1155                                         LPC_RX_TRANSFER_STATE_FR08: begin
1156                                                 // Receive firmware cycle address -- nibble 7
1157                                                 io_address[3:0] <= lpc_data_in;
1158                                                 rx_transfer_state <= LPC_RX_TRANSFER_STATE_FR09;
1159                                         end
1160                                         LPC_RX_TRANSFER_STATE_FR09: begin
1161                                                 // Receive MSIZE field
1162                                                 fw_cycle_msize <= lpc_data_in;
1163
1164                                                 // Handle data transfer
1165                                                 if (cycle_direction == 1) begin
1166                                                         rx_transfer_state <= LPC_RX_TRANSFER_STATE_FR10;
1167
1168                                                         fw_cycle_rx_nibble_counter <= 0;
1169                                                 end else begin
1170                                                         // Start driving LAD lines
1171                                                         lpc_data_direction <= 1;
1172
1173                                                         // Assert TX cycle start flag for > 1 clock
1174                                                         start_tx_cycle <= 1;
1175
1176                                                         rx_transfer_state <= LPC_RX_TRANSFER_STATE_TR08;
1177                                                 end
1178                                         end
1179                                         LPC_RX_TRANSFER_STATE_FR10: begin
1180                                                 // Signal CPU that address is ready
1181                                                 address_ready <= 1;
1182
1183                                                 // Receive data, LSN first
1184                                                 if (!fw_cycle_rx_nibble_counter[0]) begin
1185                                                         lpc_fw_output_xfer_write_addr <= fw_cycle_rx_nibble_counter[8:1];
1186                                                         lpc_fw_output_xfer_write_data[3:0] <= lpc_data_in;
1187                                                         lpc_fw_output_xfer_write_wren <= 0;
1188                                                 end else begin
1189                                                         lpc_fw_output_xfer_write_data[7:4] <= lpc_data_in;
1190                                                         lpc_fw_output_xfer_write_wren <= 1;
1191                                                 end
1192
1193                                                 case (fw_cycle_msize)
1194                                                         4'b0000: begin
1195                                                                 if (fw_cycle_rx_nibble_counter == 0) begin
1196                                                                         // Start driving LAD lines
1197                                                                         // One cycle of delay is introduced by the register on the tristate control line,
1198                                                                         // so to avoid missed LWAIT at the LPC master output direction has to be set one
1199                                                                         // cycle "early"...
1200                                                                         lpc_data_direction <= 1;
1201                                                                 end else if (fw_cycle_rx_nibble_counter >= 1) begin
1202                                                                         // Assert TX cycle start flag for > 1 clock
1203                                                                         start_tx_cycle <= 1;
1204
1205                                                                         rx_transfer_state <= LPC_RX_TRANSFER_STATE_TR08;
1206                                                                 end
1207                                                         end
1208                                                         4'b0001: begin
1209                                                                 if (fw_cycle_rx_nibble_counter == 1) begin
1210                                                                         // Start driving LAD lines
1211                                                                         // One cycle of delay is introduced by the register on the tristate control line,
1212                                                                         // so to avoid missed LWAIT at the LPC master output direction has to be set one
1213                                                                         // cycle "early"...
1214                                                                         lpc_data_direction <= 1;
1215                                                                 end else if (fw_cycle_rx_nibble_counter >= 2) begin
1216                                                                         // Assert TX cycle start flag for > 1 clock
1217                                                                         start_tx_cycle <= 1;
1218
1219                                                                         rx_transfer_state <= LPC_RX_TRANSFER_STATE_TR08;
1220                                                                 end
1221                                                         end
1222                                                         4'b0010: begin
1223                                                                 if (fw_cycle_rx_nibble_counter == 7) begin
1224                                                                         // Start driving LAD lines
1225                                                                         // One cycle of delay is introduced by the register on the tristate control line,
1226                                                                         // so to avoid missed LWAIT at the LPC master output direction has to be set one
1227                                                                         // cycle "early"...
1228                                                                         lpc_data_direction <= 1;
1229                                                                 end else if (fw_cycle_rx_nibble_counter >= 8) begin
1230                                                                         // Assert TX cycle start flag for > 1 clock
1231                                                                         start_tx_cycle <= 1;
1232
1233                                                                         rx_transfer_state <= LPC_RX_TRANSFER_STATE_TR08;
1234                                                                 end
1235                                                         end
1236                                                         4'b0100: begin
1237                                                                 if (fw_cycle_rx_nibble_counter == 31) begin
1238                                                                         // Start driving LAD lines
1239                                                                         // One cycle of delay is introduced by the register on the tristate control line,
1240                                                                         // so to avoid missed LWAIT at the LPC master output direction has to be set one
1241                                                                         // cycle "early"...
1242                                                                         lpc_data_direction <= 1;
1243                                                                 end else if (fw_cycle_rx_nibble_counter >= 32) begin
1244                                                                         // Assert TX cycle start flag for > 1 clock
1245                                                                         start_tx_cycle <= 1;
1246
1247                                                                         rx_transfer_state <= LPC_RX_TRANSFER_STATE_TR08;
1248                                                                 end
1249                                                         end
1250                                                         4'b0111: begin
1251                                                                 if (fw_cycle_rx_nibble_counter == 255) begin
1252                                                                         // Start driving LAD lines
1253                                                                         // One cycle of delay is introduced by the register on the tristate control line,
1254                                                                         // so to avoid missed LWAIT at the LPC master output direction has to be set one
1255                                                                         // cycle "early"...
1256                                                                         lpc_data_direction <= 1;
1257                                                                 end else if (fw_cycle_rx_nibble_counter >= 256) begin
1258                                                                         // Assert TX cycle start flag for > 1 clock
1259                                                                         start_tx_cycle <= 1;
1260
1261                                                                         rx_transfer_state <= LPC_RX_TRANSFER_STATE_TR08;
1262                                                                 end
1263                                                         end
1264                                                         default: begin
1265                                                                 // Disallowed size codeword
1266                                                                 // Abort cycle and signal exception
1267                                                                 rx_transfer_state <= LPC_RX_TRANSFER_STATE_IDLE;
1268
1269                                                                 // Signal exception to CPU
1270                                                                 if (!exception_ack) begin
1271                                                                         exception[2] <= 1;
1272                                                                 end
1273                                                         end
1274                                                 endcase
1275
1276                                                 fw_cycle_rx_nibble_counter <= fw_cycle_rx_nibble_counter + 1;
1277                                         end
1278                                         default: begin
1279                                                 // Not reachable under normal operation!
1280                                                 rx_transfer_state <= LPC_RX_TRANSFER_STATE_IDLE;
1281                                         end
1282                                 endcase
1283
1284                                 if (rx_transfer_state != LPC_RX_TRANSFER_STATE_IW01) begin
1285                                         // Handle asynchronous IPMI BT interface handshake signals
1286                                         if (ipmi_bt_bmc_to_host_ctl_sms_ack_cont) begin
1287                                                 ipmi_bt_bmc_to_host_ctl_sms_ack_reg <= 0;
1288                                         end
1289                                         if (ipmi_bt_bmc_to_host_ctl_attn_ack_cont) begin
1290                                                 ipmi_bt_bmc_to_host_ctl_attn_ack_reg <= 0;
1291                                         end
1292                                         if (ipmi_bt_host_to_bmc_ctl_attn_req_cont) begin
1293                                                 ipmi_bt_host_to_bmc_ctl_attn_req_reg <= 0;
1294                                         end
1295                                         if (ipmi_bt_host_to_bmc_ctl_oem0_req_cont) begin
1296                                                 ipmi_bt_host_to_bmc_ctl_oem0_req_reg <= 0;
1297                                         end
1298                                         if (ipmi_bt_irq_ack_cont) begin
1299                                                 ipmi_bt_irq_ack_reg <= 0;
1300                                         end
1301                                 end
1302
1303                                 if (exception_ack) begin
1304                                         exception <= 0;
1305                                 end
1306                         end
1307                 end
1308
1309                 // VUART IRQ signalling handlers
1310                 if (vuart1_rx_fifo_rpop_reg) begin
1311                         vuart1_rx_fifo_read_timeout_counter <= 0;
1312                         vuart1_rx_data_queue_contents_read_timeout <= 0;
1313                 end else begin
1314                         if (vuart1_rx_fifo_empty) begin
1315                                 vuart1_rx_fifo_read_timeout_counter <= 0;
1316                                 vuart1_rx_data_queue_contents_read_timeout <= 0;
1317                         end else begin
1318                                 // NOTE
1319                                 // This deviates intentionally from the 16550 UART timeouts to keep overall logic simple
1320                                 // In a VUART situation we don't care that much about exact character timing, since we'll continue
1321                                 // to eat up bytes until the FIFOs are full.
1322                                 // Use 10us as a reasonable value for the timeout here (slightly longer than 1 character time at 115200 baud)
1323                                 if (vuart1_rx_fifo_read_timeout_counter > 333) begin
1324                                         vuart1_rx_data_queue_contents_read_timeout <= 1;
1325                                 end else begin
1326                                         vuart1_rx_fifo_read_timeout_counter <= vuart1_rx_fifo_read_timeout_counter + 1;
1327                                 end
1328                         end
1329                 end
1330                 if (vuart2_rx_fifo_rpop_reg) begin
1331                         vuart2_rx_fifo_read_timeout_counter <= 0;
1332                         vuart2_rx_data_queue_contents_read_timeout <= 0;
1333                 end else begin
1334                         if (vuart2_rx_fifo_empty) begin
1335                                 vuart2_rx_fifo_read_timeout_counter <= 0;
1336                                 vuart2_rx_data_queue_contents_read_timeout <= 0;
1337                         end else begin
1338                                 // NOTE
1339                                 // This deviates intentionally from the 16550 UART timeouts to keep overall logic simple
1340                                 // In a VUART situation we don't care that much about exact character timing, since we'll continue
1341                                 // to eat up bytes until the FIFOs are full.
1342                                 // Use 10us as a reasonable value for the timeout here (slightly longer than 1 character time at 115200 baud)
1343                                 if (vuart2_rx_fifo_read_timeout_counter > 333) begin
1344                                         vuart2_rx_data_queue_contents_read_timeout <= 1;
1345                                 end else begin
1346                                         vuart2_rx_fifo_read_timeout_counter <= vuart2_rx_fifo_read_timeout_counter + 1;
1347                                 end
1348                         end
1349                 end
1350                 case (vuart1_rcvr_trigger)
1351                         2'b00: begin
1352                                 if ((vuart1_rx_data_available_count >= 1) || vuart1_rx_fifo_full) begin
1353                                         vuart1_rx_data_queue_contents_past_trigger <= 1;
1354                                 end else begin
1355                                         vuart1_rx_data_queue_contents_past_trigger <= 0;
1356                                 end
1357                         end
1358                         2'b01: begin
1359                                 if ((vuart1_rx_data_available_count >= 4) || vuart1_rx_fifo_full) begin
1360                                         vuart1_rx_data_queue_contents_past_trigger <= 1;
1361                                 end else begin
1362                                         vuart1_rx_data_queue_contents_past_trigger <= 0;
1363                                 end
1364                         end
1365                         2'b10: begin
1366                                 if ((vuart1_rx_data_available_count >= 8) || vuart1_rx_fifo_full) begin
1367                                         vuart1_rx_data_queue_contents_past_trigger <= 1;
1368                                 end else begin
1369                                         vuart1_rx_data_queue_contents_past_trigger <= 0;
1370                                 end
1371                         end
1372                         2'b11: begin
1373                                 if ((vuart1_rx_data_available_count >= 14) || vuart1_rx_fifo_full) begin
1374                                         vuart1_rx_data_queue_contents_past_trigger <= 1;
1375                                 end else begin
1376                                         vuart1_rx_data_queue_contents_past_trigger <= 0;
1377                                 end
1378                         end
1379                 endcase
1380                 case (vuart2_rcvr_trigger)
1381                         2'b00: begin
1382                                 if ((vuart2_rx_data_available_count >= 1) || vuart2_rx_fifo_full) begin
1383                                         vuart2_rx_data_queue_contents_past_trigger <= 1;
1384                                 end else begin
1385                                         vuart2_rx_data_queue_contents_past_trigger <= 0;
1386                                 end
1387                         end
1388                         2'b01: begin
1389                                 if ((vuart2_rx_data_available_count >= 4) || vuart2_rx_fifo_full) begin
1390                                         vuart2_rx_data_queue_contents_past_trigger <= 1;
1391                                 end else begin
1392                                         vuart2_rx_data_queue_contents_past_trigger <= 0;
1393                                 end
1394                         end
1395                         2'b10: begin
1396                                 if ((vuart2_rx_data_available_count >= 8) || vuart2_rx_fifo_full) begin
1397                                         vuart2_rx_data_queue_contents_past_trigger <= 1;
1398                                 end else begin
1399                                         vuart2_rx_data_queue_contents_past_trigger <= 0;
1400                                 end
1401                         end
1402                         2'b11: begin
1403                                 if ((vuart2_rx_data_available_count >= 14) || vuart2_rx_fifo_full) begin
1404                                         vuart2_rx_data_queue_contents_past_trigger <= 1;
1405                                 end else begin
1406                                         vuart2_rx_data_queue_contents_past_trigger <= 0;
1407                                 end
1408                         end
1409                 endcase
1410
1411                 if (vuart1_ier[2] && vuart1_rx_break_irq_pending) begin
1412                         vuart1_interrupt_pending <= 1;
1413                         vuart1_interrupt_id <= 3'b010;
1414                 end else if (vuart1_ier[0] && vuart1_rx_data_queue_contents_past_trigger) begin
1415                         vuart1_interrupt_pending <= 1;
1416                         vuart1_interrupt_id <= 3'b010;
1417                 end else if (vuart1_ier[0] && vuart1_rx_data_queue_contents_read_timeout) begin
1418                         vuart1_interrupt_pending <= 1;
1419                         vuart1_interrupt_id <= 3'b110;
1420                 end else if (vuart1_ier[1] && vuart1_tx_fifo_empty_irq_pending) begin
1421                         vuart1_interrupt_pending <= 1;
1422                         vuart1_interrupt_id <= 3'b001;
1423                 end else begin
1424                         vuart1_interrupt_pending <= 0;
1425                         vuart1_interrupt_id <= 3'b000;
1426                 end
1427
1428                 if (vuart1_tx_fifo_wren_reg || vuart1_iir_read_tx_empty_assert) begin
1429                         vuart1_tx_fifo_empty_irq_pending <= 0;
1430                 end else begin
1431                         if (vuart1_tx_fifo_empty && !vuart1_tx_fifo_empty_prev) begin
1432                                 vuart1_tx_fifo_empty_irq_pending <= 1;
1433                         end
1434                 end
1435                 if (vuart1_lsr_read_assert || !vuart1_control_register[0]) begin
1436                         vuart1_rx_break_irq_pending <= 0;
1437                 end else begin
1438                         if (vuart1_control_register[0] && !vuart1_rx_break_request_prev) begin
1439                                 vuart1_rx_break_irq_pending <= 1;
1440                         end
1441                 end
1442
1443                 if (vuart2_ier[2] && vuart2_rx_break_irq_pending) begin
1444                         vuart2_interrupt_pending <= 1;
1445                         vuart2_interrupt_id <= 3'b010;
1446                 end else if (vuart2_ier[0] && vuart2_rx_data_queue_contents_past_trigger) begin
1447                         vuart2_interrupt_pending <= 1;
1448                         vuart2_interrupt_id <= 3'b010;
1449                 end else if (vuart2_ier[0] && vuart2_rx_data_queue_contents_read_timeout) begin
1450                         vuart2_interrupt_pending <= 1;
1451                         vuart2_interrupt_id <= 3'b110;
1452                 end else if (vuart2_ier[1] && vuart2_tx_fifo_empty_irq_pending) begin
1453                         vuart2_interrupt_pending <= 1;
1454                         vuart2_interrupt_id <= 3'b001;
1455                 end else begin
1456                         vuart2_interrupt_pending <= 0;
1457                         vuart2_interrupt_id <= 3'b000;
1458                 end
1459
1460                 if (vuart2_tx_fifo_wren_reg || vuart2_iir_read_tx_empty_assert) begin
1461                         vuart2_tx_fifo_empty_irq_pending <= 0;
1462                 end else begin
1463                         if (vuart2_tx_fifo_empty && !vuart2_tx_fifo_empty_prev) begin
1464                                 vuart2_tx_fifo_empty_irq_pending <= 1;
1465                         end
1466                 end
1467                 if (vuart2_lsr_read_assert || !vuart2_control_register[0]) begin
1468                         vuart2_rx_break_irq_pending <= 0;
1469                 end else begin
1470                         if (vuart2_control_register[0] && !vuart2_rx_break_request_prev) begin
1471                                 vuart2_rx_break_irq_pending <= 1;
1472                         end
1473                 end
1474
1475                 if (vuart1_iir_read_tx_empty_assert) begin
1476                         vuart1_iir_read_tx_empty_assert <= 0;
1477                 end
1478                 if (vuart2_iir_read_tx_empty_assert) begin
1479                         vuart2_iir_read_tx_empty_assert <= 0;
1480                 end
1481
1482                 if (!vuart1_control_register[0]) begin
1483                         vuart1_assert_b2h_break_clear_reg <= 0;
1484                 end
1485                 if (!vuart2_control_register[0]) begin
1486                         vuart2_assert_b2h_break_clear_reg <= 0;
1487                 end
1488                 if (vuart1_lsr_read_assert) begin
1489                         vuart1_lsr_read_assert <= 0;
1490                 end
1491                 if (vuart2_lsr_read_assert) begin
1492                         vuart2_lsr_read_assert <= 0;
1493                 end
1494
1495                 vuart1_tx_fifo_empty_prev <= vuart1_tx_fifo_empty;
1496                 vuart2_tx_fifo_empty_prev <= vuart2_tx_fifo_empty;
1497                 vuart1_rx_break_request_prev <= vuart1_control_register[0];
1498                 vuart2_rx_break_request_prev <= vuart2_control_register[0];
1499                 lpc_frame_n_prev <= lpc_frame_n;
1500         end
1501
1502         reg start_tx_cycle_reg_tx = 0;
1503         reg abort_tx_cycle_reg_tx = 0;
1504         reg data_ack_reg_tx = 0;
1505         reg continue_reg_tx = 0;
1506         reg special_data_ack_reg_tx = 0;
1507         reg special_continue_reg_tx = 0;
1508         reg read_is_special_tx = 0;
1509         reg [7:0] lpc_tx_data_buffer = 0;
1510         reg [7:0] cycle_completion_codeword = 0;
1511
1512         always @(posedge lpc_clock) begin
1513                 // Avoid logic glitches due to these signals crossing clock domains
1514                 start_tx_cycle_reg_tx <= start_tx_cycle;
1515                 abort_tx_cycle_reg_tx <= abort_tx_cycle;
1516                 data_ack_reg_tx <= data_ack;
1517                 continue_reg_tx <= continue;
1518                 special_data_ack_reg_tx <= rx_special_data_ack;
1519                 special_continue_reg_tx <= rx_special_continue;
1520
1521                 if (abort_tx_cycle_reg_tx) begin
1522                         tx_transfer_state <= LPC_TX_TRANSFER_STATE_IDLE;
1523                 end else begin
1524                         case (tx_transfer_state)
1525                                 LPC_TX_TRANSFER_STATE_IDLE: begin
1526                                         if (start_tx_cycle_reg_tx) begin
1527                                                 if (cycle_direction == 1) begin
1528                                                         tx_transfer_state <= LPC_TX_TRANSFER_STATE_TR01;
1529                                                 end else begin
1530                                                         if (firmware_cycle) begin
1531                                                                 tx_transfer_state <= LPC_TX_TRANSFER_STATE_FR01;
1532                                                         end else begin
1533                                                                 tx_transfer_state <= LPC_TX_TRANSFER_STATE_TR04;
1534                                                         end
1535                                                 end
1536                                         end
1537
1538                                         data_ready_cont <= 0;
1539                                         continue_cont <= 0;
1540                                         tx_cycle_done <= 0;
1541
1542                                         // Drive LWAIT by default
1543                                         lpc_data_out <= LPC_CODEWORD_SYNC_LWAIT;
1544                                 end
1545                                 LPC_TX_TRANSFER_STATE_TR01: begin
1546                                         if (data_ack_reg_tx || special_data_ack_reg_tx) begin
1547                                                 data_ready_cont <= 1;
1548                                                 if (transfer_error && !special_data_ack_reg_tx) begin
1549                                                         cycle_completion_codeword <= LPC_CODEWORD_SYNC_ERROR;
1550                                                 end else begin
1551                                                         cycle_completion_codeword <= LPC_CODEWORD_SYNC_READY;
1552                                                 end
1553                                                 tx_transfer_state <= LPC_TX_TRANSFER_STATE_TR02;
1554                                         end
1555
1556                                         // Drive LWAIT
1557                                         lpc_data_out <= LPC_CODEWORD_SYNC_LWAIT;
1558                                 end
1559                                 LPC_TX_TRANSFER_STATE_TR02: begin
1560                                         if (!data_ack_reg_tx && !special_data_ack_reg_tx) begin
1561                                                 data_ready_cont <= 0;
1562                                                 tx_transfer_state <= LPC_TX_TRANSFER_STATE_TR03;
1563                                         end
1564
1565                                         // Drive LWAIT
1566                                         lpc_data_out <= LPC_CODEWORD_SYNC_LWAIT;
1567                                 end
1568                                 LPC_TX_TRANSFER_STATE_TR03: begin
1569                                         // Drive sync
1570                                         tx_transfer_state <= LPC_TX_TRANSFER_STATE_TR09;
1571
1572                                         // Drive sync
1573                                         lpc_data_out <= cycle_completion_codeword;
1574                                 end
1575                                 LPC_TX_TRANSFER_STATE_TR04: begin
1576                                         if (continue_reg_tx || special_continue_reg_tx) begin
1577                                                 continue_cont <= 1;
1578                                                 if (transfer_error && !special_continue_reg_tx) begin
1579                                                         cycle_completion_codeword <= LPC_CODEWORD_SYNC_ERROR;
1580                                                 end else begin
1581                                                         cycle_completion_codeword <= LPC_CODEWORD_SYNC_READY;
1582                                                 end
1583                                                 tx_transfer_state <= LPC_TX_TRANSFER_STATE_TR05;
1584                                         end
1585
1586                                         if (special_continue_reg_tx) begin
1587                                                 read_is_special_tx <= 1;
1588                                         end else begin
1589                                                 read_is_special_tx <= 0;
1590                                         end
1591
1592                                         // Drive LWAIT
1593                                         lpc_data_out <= LPC_CODEWORD_SYNC_LWAIT;
1594                                 end
1595                                 LPC_TX_TRANSFER_STATE_TR05: begin
1596                                         if (!continue_reg_tx && !special_continue_reg_tx) begin
1597                                                 continue_cont <= 0;
1598                                                 tx_transfer_state <= LPC_TX_TRANSFER_STATE_TR06;
1599                                         end
1600
1601                                         // Drive LWAIT
1602                                         lpc_data_out <= LPC_CODEWORD_SYNC_LWAIT;
1603                                 end
1604                                 LPC_TX_TRANSFER_STATE_TR06: begin
1605                                         // Drive sync
1606                                         tx_transfer_state <= LPC_TX_TRANSFER_STATE_TR07;
1607
1608                                         // Drive sync
1609                                         lpc_data_out <= cycle_completion_codeword;
1610                                 end
1611                                 LPC_TX_TRANSFER_STATE_TR07: begin
1612                                         // Transmit first nibble of I/O data
1613                                         tx_transfer_state <= LPC_TX_TRANSFER_STATE_TR08;
1614
1615                                         // Transmit first nibble of I/O data
1616                                         if (read_is_special_tx) begin
1617                                                 lpc_data_out <= special_tx_data[3:0];
1618                                         end else begin
1619                                                 lpc_data_out <= tx_data[3:0];
1620                                         end
1621                                 end
1622                                 LPC_TX_TRANSFER_STATE_TR08: begin
1623                                         // Transmit second nibble of I/O data
1624                                         tx_transfer_state <= LPC_TX_TRANSFER_STATE_TR09;
1625
1626                                         // Transmit second nibble of I/O data
1627                                         if (read_is_special_tx) begin
1628                                                 lpc_data_out <= special_tx_data[7:4];
1629                                         end else begin
1630                                                 lpc_data_out <= tx_data[7:4];
1631                                         end
1632                                 end
1633                                 LPC_TX_TRANSFER_STATE_TR09: begin
1634                                         // Drive turn-around cycle part 1
1635                                         tx_transfer_state <= LPC_TX_TRANSFER_STATE_TR10;
1636
1637                                         // Drive turn-around cycle part 1
1638                                         lpc_data_out <= LPC_CODEWORD_TURNAROUND;
1639                                 end
1640                                 LPC_TX_TRANSFER_STATE_TR10: begin
1641                                         // Drive turn-around cycle part 2
1642                                         tx_transfer_state <= LPC_TX_TRANSFER_STATE_TR11;
1643                                         tx_cycle_done <= 1;
1644
1645                                         // Drive turn-around cycle part 2
1646                                         lpc_data_out <= LPC_CODEWORD_TURNAROUND;
1647                                 end
1648                                 LPC_TX_TRANSFER_STATE_TR11: begin
1649                                         // Assert done flag for > 1 clock, then return to idle
1650                                         tx_transfer_state <= LPC_TX_TRANSFER_STATE_IDLE;
1651
1652                                         // Keep driving turn-around cycle during I/O direction switch
1653                                         lpc_data_out <= LPC_CODEWORD_TURNAROUND;
1654                                 end
1655                                 LPC_TX_TRANSFER_STATE_FR01: begin
1656                                         if (continue_reg_tx) begin
1657                                                 continue_cont <= 1;
1658                                                 tx_transfer_state <= LPC_TX_TRANSFER_STATE_FR02;
1659                                         end
1660
1661                                         // Drive LWAIT
1662                                         lpc_data_out <= LPC_CODEWORD_SYNC_LWAIT;
1663                                 end
1664                                 LPC_TX_TRANSFER_STATE_FR02: begin
1665                                         if (!continue_reg_tx) begin
1666                                                 continue_cont <= 0;
1667                                                 tx_transfer_state <= LPC_TX_TRANSFER_STATE_FR03;
1668                                         end
1669
1670                                         // Set up transfer
1671                                         lpc_fw_input_xfer_read_addr <= 0;
1672                                         fw_cycle_tx_byte_counter <= 0;
1673
1674                                         // Drive LWAIT
1675                                         lpc_data_out <= LPC_CODEWORD_SYNC_LWAIT;
1676                                 end
1677                                 LPC_TX_TRANSFER_STATE_FR03: begin
1678                                         // Drive sync
1679                                         tx_transfer_state <= LPC_TX_TRANSFER_STATE_FR04;
1680
1681                                         // Drive sync
1682                                         lpc_data_out <= LPC_CODEWORD_SYNC_READY;
1683                                 end
1684                                 LPC_TX_TRANSFER_STATE_FR04: begin
1685                                         // Drive first nibble in TX state machine, then set up next byte read from RAM
1686                                         tx_transfer_state <= LPC_TX_TRANSFER_STATE_FR05;
1687
1688                                         lpc_tx_data_buffer <= lpc_fw_input_xfer_read_data;
1689                                         fw_cycle_tx_byte_counter <= fw_cycle_tx_byte_counter + 1;
1690                                         lpc_fw_input_xfer_read_addr <= fw_cycle_tx_byte_counter + 1;
1691
1692                                         // Transmit first nibble of FW data byte
1693                                         lpc_data_out <= lpc_fw_input_xfer_read_data[3:0];
1694                                 end
1695                                 LPC_TX_TRANSFER_STATE_FR05: begin
1696                                         // Drive second nibble in TX state machine
1697                                         case (fw_cycle_msize)
1698                                                 4'b0000: begin
1699                                                         tx_transfer_state <= LPC_TX_TRANSFER_STATE_TR09;
1700                                                 end
1701                                                 4'b0001: begin
1702                                                         if (fw_cycle_tx_byte_counter >= 1) begin
1703                                                                 tx_transfer_state <= LPC_TX_TRANSFER_STATE_TR09;
1704                                                         end else begin
1705                                                                 tx_transfer_state <= LPC_TX_TRANSFER_STATE_FR04;
1706                                                         end
1707                                                 end
1708                                                 4'b0010: begin
1709                                                         if (fw_cycle_tx_byte_counter >= 4) begin
1710                                                                 tx_transfer_state <= LPC_TX_TRANSFER_STATE_TR09;
1711                                                         end else begin
1712                                                                 tx_transfer_state <= LPC_TX_TRANSFER_STATE_FR04;
1713                                                         end
1714                                                 end
1715                                                 4'b0100: begin
1716                                                         if (fw_cycle_tx_byte_counter >= 16) begin
1717                                                                 tx_transfer_state <= LPC_TX_TRANSFER_STATE_TR09;
1718                                                         end else begin
1719                                                                 tx_transfer_state <= LPC_TX_TRANSFER_STATE_FR04;
1720                                                         end
1721                                                 end
1722                                                 4'b0111: begin
1723                                                         if (fw_cycle_tx_byte_counter >= 128) begin
1724                                                                 tx_transfer_state <= LPC_TX_TRANSFER_STATE_TR09;
1725                                                         end else begin
1726                                                                 tx_transfer_state <= LPC_TX_TRANSFER_STATE_FR04;
1727                                                         end
1728                                                 end
1729                                                 default: begin
1730                                                         // Disallowed size codeword
1731                                                         // Abort cycle
1732                                                         tx_transfer_state <= LPC_TX_TRANSFER_STATE_TR09;
1733                                                 end
1734                                         endcase
1735
1736                                         // Transmit second nibble of FW data byte
1737                                         lpc_data_out <= lpc_tx_data_buffer[7:4];
1738                                 end
1739                                 default: begin
1740                                         // Should never reach this point!
1741                                         // In case of a glitch into this state, drive
1742                                         // turnaround in preparation to unlock bus...
1743                                         tx_transfer_state <= LPC_TX_TRANSFER_STATE_TR09;
1744
1745                                         // Drive LWAIT
1746                                         lpc_data_out <= LPC_CODEWORD_SYNC_LWAIT;
1747                                 end
1748                         endcase
1749                 end
1750         end
1751
1752         PDPW16KD #(
1753                 .INITVAL_00(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1754                 .INITVAL_01(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1755                 .INITVAL_02(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1756                 .INITVAL_03(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1757                 .INITVAL_04(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1758                 .INITVAL_05(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1759                 .INITVAL_06(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1760                 .INITVAL_07(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1761                 .INITVAL_08(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1762                 .INITVAL_09(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1763                 .INITVAL_0A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1764                 .INITVAL_0B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1765                 .INITVAL_0C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1766                 .INITVAL_0D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1767                 .INITVAL_0E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1768                 .INITVAL_0F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1769                 .INITVAL_10(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1770                 .INITVAL_11(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1771                 .INITVAL_12(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1772                 .INITVAL_13(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1773                 .INITVAL_14(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1774                 .INITVAL_15(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1775                 .INITVAL_16(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1776                 .INITVAL_17(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1777                 .INITVAL_18(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1778                 .INITVAL_19(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1779                 .INITVAL_1A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1780                 .INITVAL_1B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1781                 .INITVAL_1C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1782                 .INITVAL_1D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1783                 .INITVAL_1E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1784                 .INITVAL_1F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1785                 .INITVAL_20(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1786                 .INITVAL_21(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1787                 .INITVAL_22(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1788                 .INITVAL_23(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1789                 .INITVAL_24(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1790                 .INITVAL_25(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1791                 .INITVAL_26(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1792                 .INITVAL_27(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1793                 .INITVAL_28(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1794                 .INITVAL_29(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1795                 .INITVAL_2A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1796                 .INITVAL_2B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1797                 .INITVAL_2C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1798                 .INITVAL_2D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1799                 .INITVAL_2E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1800                 .INITVAL_2F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1801                 .INITVAL_30(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1802                 .INITVAL_31(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1803                 .INITVAL_32(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1804                 .INITVAL_33(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1805                 .INITVAL_34(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1806                 .INITVAL_35(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1807                 .INITVAL_36(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1808                 .INITVAL_37(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1809                 .INITVAL_38(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1810                 .INITVAL_39(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1811                 .INITVAL_3A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1812                 .INITVAL_3B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1813                 .INITVAL_3C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1814                 .INITVAL_3D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1815                 .INITVAL_3E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1816                 .INITVAL_3F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1817                 // Ordinarily this would be 2048 elements deep, 9 bits wide, but Yosys doesn't have support
1818                 // for bit widths other than 36 (https://github.com/YosysHQ/yosys/issues/2143)
1819                 // Since we don't need 2048 (or even 512) elements here, run it in 36 bit data mode with 512 elements
1820                 .DATA_WIDTH_W(36),
1821                 .DATA_WIDTH_R(36)
1822         ) lpc_fw_cycle_input_xfer_bram(
1823                 .BE3(1'b1),
1824                 .BE2(1'b1),
1825                 .BE1(1'b1),
1826                 .BE0(1'b1),
1827                 .DI7(lpc_fw_input_xfer_write_data[7]),
1828                 .DI6(lpc_fw_input_xfer_write_data[6]),
1829                 .DI5(lpc_fw_input_xfer_write_data[5]),
1830                 .DI4(lpc_fw_input_xfer_write_data[4]),
1831                 .DI3(lpc_fw_input_xfer_write_data[3]),
1832                 .DI2(lpc_fw_input_xfer_write_data[2]),
1833                 .DI1(lpc_fw_input_xfer_write_data[1]),
1834                 .DI0(lpc_fw_input_xfer_write_data[0]),
1835                 .CSW2(1'b0),
1836                 .CSW1(1'b0),
1837                 .CSW0(1'b0),
1838                 .ADW8(lpc_fw_input_xfer_write_addr[8]),
1839                 .ADW7(lpc_fw_input_xfer_write_addr[7]),
1840                 .ADW6(lpc_fw_input_xfer_write_addr[6]),
1841                 .ADW5(lpc_fw_input_xfer_write_addr[5]),
1842                 .ADW4(lpc_fw_input_xfer_write_addr[4]),
1843                 .ADW3(lpc_fw_input_xfer_write_addr[3]),
1844                 .ADW2(lpc_fw_input_xfer_write_addr[2]),
1845                 .ADW1(lpc_fw_input_xfer_write_addr[1]),
1846                 .ADW0(lpc_fw_input_xfer_write_addr[0]),
1847                 // NOTE
1848                 // The ECP5 block RAMs operate in a non-intuitive manner.
1849                 // To connect both ports to the same set of memory cells, one port has to be attached
1850                 // 1:1 in address and data lines, while the other is offset (data + 18, address + 5).
1851                 .DO25(lpc_fw_input_xfer_read_data[7]),
1852                 .DO24(lpc_fw_input_xfer_read_data[6]),
1853                 .DO23(lpc_fw_input_xfer_read_data[5]),
1854                 .DO22(lpc_fw_input_xfer_read_data[4]),
1855                 .DO21(lpc_fw_input_xfer_read_data[3]),
1856                 .DO20(lpc_fw_input_xfer_read_data[2]),
1857                 .DO19(lpc_fw_input_xfer_read_data[1]),
1858                 .DO18(lpc_fw_input_xfer_read_data[0]),
1859                 .CSR2(1'b0),
1860                 .CSR1(1'b0),
1861                 .CSR0(1'b0),
1862                 .ADR13(lpc_fw_input_xfer_read_addr[8]),
1863                 .ADR12(lpc_fw_input_xfer_read_addr[7]),
1864                 .ADR11(lpc_fw_input_xfer_read_addr[6]),
1865                 .ADR10(lpc_fw_input_xfer_read_addr[5]),
1866                 .ADR9(lpc_fw_input_xfer_read_addr[4]),
1867                 .ADR8(lpc_fw_input_xfer_read_addr[3]),
1868                 .ADR7(lpc_fw_input_xfer_read_addr[2]),
1869                 .ADR6(lpc_fw_input_xfer_read_addr[1]),
1870                 .ADR5(lpc_fw_input_xfer_read_addr[0]),
1871                 .ADR4(1'b0),
1872                 .ADR3(1'b0),
1873                 .ADR2(1'b0),
1874                 .ADR1(1'b0),
1875                 .ADR0(1'b0),
1876                 .CEW(lpc_fw_input_xfer_write_wren),
1877                 .CLKW(lpc_fw_input_xfer_write_clk),
1878                 .CER(1'b1),
1879                 .CLKR(lpc_clock),
1880                 .OCER(1'b1),
1881                 .RST(1'b0)
1882         );
1883
1884         PDPW16KD #(
1885                 .INITVAL_00(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1886                 .INITVAL_01(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1887                 .INITVAL_02(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1888                 .INITVAL_03(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1889                 .INITVAL_04(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1890                 .INITVAL_05(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1891                 .INITVAL_06(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1892                 .INITVAL_07(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1893                 .INITVAL_08(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1894                 .INITVAL_09(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1895                 .INITVAL_0A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1896                 .INITVAL_0B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1897                 .INITVAL_0C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1898                 .INITVAL_0D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1899                 .INITVAL_0E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1900                 .INITVAL_0F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1901                 .INITVAL_10(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1902                 .INITVAL_11(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1903                 .INITVAL_12(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1904                 .INITVAL_13(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1905                 .INITVAL_14(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1906                 .INITVAL_15(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1907                 .INITVAL_16(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1908                 .INITVAL_17(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1909                 .INITVAL_18(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1910                 .INITVAL_19(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1911                 .INITVAL_1A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1912                 .INITVAL_1B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1913                 .INITVAL_1C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1914                 .INITVAL_1D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1915                 .INITVAL_1E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1916                 .INITVAL_1F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1917                 .INITVAL_20(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1918                 .INITVAL_21(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1919                 .INITVAL_22(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1920                 .INITVAL_23(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1921                 .INITVAL_24(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1922                 .INITVAL_25(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1923                 .INITVAL_26(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1924                 .INITVAL_27(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1925                 .INITVAL_28(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1926                 .INITVAL_29(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1927                 .INITVAL_2A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1928                 .INITVAL_2B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1929                 .INITVAL_2C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1930                 .INITVAL_2D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1931                 .INITVAL_2E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1932                 .INITVAL_2F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1933                 .INITVAL_30(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1934                 .INITVAL_31(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1935                 .INITVAL_32(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1936                 .INITVAL_33(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1937                 .INITVAL_34(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1938                 .INITVAL_35(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1939                 .INITVAL_36(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1940                 .INITVAL_37(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1941                 .INITVAL_38(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1942                 .INITVAL_39(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1943                 .INITVAL_3A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1944                 .INITVAL_3B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1945                 .INITVAL_3C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1946                 .INITVAL_3D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1947                 .INITVAL_3E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1948                 .INITVAL_3F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
1949                 // Ordinarily this would be 2048 elements deep, 9 bits wide, but Yosys doesn't have support
1950                 // for bit widths other than 36 (https://github.com/YosysHQ/yosys/issues/2143)
1951                 // Since we don't need 2048 (or even 512) elements here, run it in 36 bit data mode with 512 elements
1952                 .DATA_WIDTH_W(36),
1953                 .DATA_WIDTH_R(36)
1954         ) lpc_fw_cycle_output_xfer_bram(
1955                 .BE3(1'b1),
1956                 .BE2(1'b1),
1957                 .BE1(1'b1),
1958                 .BE0(1'b1),
1959                 .DI7(lpc_fw_output_xfer_write_data[7]),
1960                 .DI6(lpc_fw_output_xfer_write_data[6]),
1961                 .DI5(lpc_fw_output_xfer_write_data[5]),
1962                 .DI4(lpc_fw_output_xfer_write_data[4]),
1963                 .DI3(lpc_fw_output_xfer_write_data[3]),
1964                 .DI2(lpc_fw_output_xfer_write_data[2]),
1965                 .DI1(lpc_fw_output_xfer_write_data[1]),
1966                 .DI0(lpc_fw_output_xfer_write_data[0]),
1967                 .CSW2(1'b0),
1968                 .CSW1(1'b0),
1969                 .CSW0(1'b0),
1970                 .ADW8(lpc_fw_output_xfer_write_addr[8]),
1971                 .ADW7(lpc_fw_output_xfer_write_addr[7]),
1972                 .ADW6(lpc_fw_output_xfer_write_addr[6]),
1973                 .ADW5(lpc_fw_output_xfer_write_addr[5]),
1974                 .ADW4(lpc_fw_output_xfer_write_addr[4]),
1975                 .ADW3(lpc_fw_output_xfer_write_addr[3]),
1976                 .ADW2(lpc_fw_output_xfer_write_addr[2]),
1977                 .ADW1(lpc_fw_output_xfer_write_addr[1]),
1978                 .ADW0(lpc_fw_output_xfer_write_addr[0]),
1979                 // NOTE
1980                 // The ECP5 block RAMs operate in a non-intuitive manner.
1981                 // To connect both ports to the same set of memory cells, one port has to be attached
1982                 // 1:1 in address and data lines, while the other is offset (data + 18, address + 5).
1983                 .DO25(lpc_fw_output_xfer_read_data[7]),
1984                 .DO24(lpc_fw_output_xfer_read_data[6]),
1985                 .DO23(lpc_fw_output_xfer_read_data[5]),
1986                 .DO22(lpc_fw_output_xfer_read_data[4]),
1987                 .DO21(lpc_fw_output_xfer_read_data[3]),
1988                 .DO20(lpc_fw_output_xfer_read_data[2]),
1989                 .DO19(lpc_fw_output_xfer_read_data[1]),
1990                 .DO18(lpc_fw_output_xfer_read_data[0]),
1991                 .CSR2(1'b0),
1992                 .CSR1(1'b0),
1993                 .CSR0(1'b0),
1994                 .ADR13(lpc_fw_output_xfer_read_addr[8]),
1995                 .ADR12(lpc_fw_output_xfer_read_addr[7]),
1996                 .ADR11(lpc_fw_output_xfer_read_addr[6]),
1997                 .ADR10(lpc_fw_output_xfer_read_addr[5]),
1998                 .ADR9(lpc_fw_output_xfer_read_addr[4]),
1999                 .ADR8(lpc_fw_output_xfer_read_addr[3]),
2000                 .ADR7(lpc_fw_output_xfer_read_addr[2]),
2001                 .ADR6(lpc_fw_output_xfer_read_addr[1]),
2002                 .ADR5(lpc_fw_output_xfer_read_addr[0]),
2003                 .ADR4(1'b0),
2004                 .ADR3(1'b0),
2005                 .ADR2(1'b0),
2006                 .ADR1(1'b0),
2007                 .ADR0(1'b0),
2008                 .CEW(lpc_fw_output_xfer_write_wren),
2009                 .CLKW(lpc_clock),
2010                 .CER(1'b1),
2011                 .CLKR(lpc_fw_output_xfer_read_clk),
2012                 .OCER(1'b1),
2013                 .RST(1'b0)
2014         );
2015
2016         PDPW16KD #(
2017                 .INITVAL_00(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2018                 .INITVAL_01(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2019                 .INITVAL_02(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2020                 .INITVAL_03(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2021                 .INITVAL_04(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2022                 .INITVAL_05(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2023                 .INITVAL_06(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2024                 .INITVAL_07(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2025                 .INITVAL_08(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2026                 .INITVAL_09(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2027                 .INITVAL_0A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2028                 .INITVAL_0B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2029                 .INITVAL_0C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2030                 .INITVAL_0D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2031                 .INITVAL_0E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2032                 .INITVAL_0F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2033                 .INITVAL_10(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2034                 .INITVAL_11(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2035                 .INITVAL_12(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2036                 .INITVAL_13(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2037                 .INITVAL_14(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2038                 .INITVAL_15(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2039                 .INITVAL_16(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2040                 .INITVAL_17(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2041                 .INITVAL_18(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2042                 .INITVAL_19(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2043                 .INITVAL_1A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2044                 .INITVAL_1B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2045                 .INITVAL_1C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2046                 .INITVAL_1D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2047                 .INITVAL_1E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2048                 .INITVAL_1F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2049                 .INITVAL_20(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2050                 .INITVAL_21(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2051                 .INITVAL_22(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2052                 .INITVAL_23(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2053                 .INITVAL_24(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2054                 .INITVAL_25(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2055                 .INITVAL_26(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2056                 .INITVAL_27(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2057                 .INITVAL_28(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2058                 .INITVAL_29(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2059                 .INITVAL_2A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2060                 .INITVAL_2B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2061                 .INITVAL_2C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2062                 .INITVAL_2D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2063                 .INITVAL_2E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2064                 .INITVAL_2F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2065                 .INITVAL_30(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2066                 .INITVAL_31(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2067                 .INITVAL_32(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2068                 .INITVAL_33(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2069                 .INITVAL_34(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2070                 .INITVAL_35(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2071                 .INITVAL_36(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2072                 .INITVAL_37(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2073                 .INITVAL_38(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2074                 .INITVAL_39(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2075                 .INITVAL_3A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2076                 .INITVAL_3B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2077                 .INITVAL_3C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2078                 .INITVAL_3D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2079                 .INITVAL_3E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2080                 .INITVAL_3F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2081                 // Ordinarily this would be 2048 elements deep, 9 bits wide, but Yosys doesn't have support
2082                 // for bit widths other than 36 (https://github.com/YosysHQ/yosys/issues/2143)
2083                 // Since we don't need 2048 (or even 512) elements here, run it in 36 bit data mode with 512 elements
2084                 .DATA_WIDTH_W(36),
2085                 .DATA_WIDTH_R(36)
2086         ) ipmi_bt_cycle_input_xfer_bram(
2087                 .BE3(1'b1),
2088                 .BE2(1'b1),
2089                 .BE1(1'b1),
2090                 .BE0(1'b1),
2091                 .DI7(ipmi_bt_input_xfer_write_data[7]),
2092                 .DI6(ipmi_bt_input_xfer_write_data[6]),
2093                 .DI5(ipmi_bt_input_xfer_write_data[5]),
2094                 .DI4(ipmi_bt_input_xfer_write_data[4]),
2095                 .DI3(ipmi_bt_input_xfer_write_data[3]),
2096                 .DI2(ipmi_bt_input_xfer_write_data[2]),
2097                 .DI1(ipmi_bt_input_xfer_write_data[1]),
2098                 .DI0(ipmi_bt_input_xfer_write_data[0]),
2099                 .CSW2(1'b0),
2100                 .CSW1(1'b0),
2101                 .CSW0(1'b0),
2102                 .ADW8(ipmi_bt_input_xfer_write_addr[8]),
2103                 .ADW7(ipmi_bt_input_xfer_write_addr[7]),
2104                 .ADW6(ipmi_bt_input_xfer_write_addr[6]),
2105                 .ADW5(ipmi_bt_input_xfer_write_addr[5]),
2106                 .ADW4(ipmi_bt_input_xfer_write_addr[4]),
2107                 .ADW3(ipmi_bt_input_xfer_write_addr[3]),
2108                 .ADW2(ipmi_bt_input_xfer_write_addr[2]),
2109                 .ADW1(ipmi_bt_input_xfer_write_addr[1]),
2110                 .ADW0(ipmi_bt_input_xfer_write_addr[0]),
2111                 // NOTE
2112                 // The ECP5 block RAMs operate in a non-intuitive manner.
2113                 // To connect both ports to the same set of memory cells, one port has to be attached
2114                 // 1:1 in address and data lines, while the other is offset (data + 18, address + 5).
2115                 .DO25(ipmi_bt_input_xfer_read_data[7]),
2116                 .DO24(ipmi_bt_input_xfer_read_data[6]),
2117                 .DO23(ipmi_bt_input_xfer_read_data[5]),
2118                 .DO22(ipmi_bt_input_xfer_read_data[4]),
2119                 .DO21(ipmi_bt_input_xfer_read_data[3]),
2120                 .DO20(ipmi_bt_input_xfer_read_data[2]),
2121                 .DO19(ipmi_bt_input_xfer_read_data[1]),
2122                 .DO18(ipmi_bt_input_xfer_read_data[0]),
2123                 .CSR2(1'b0),
2124                 .CSR1(1'b0),
2125                 .CSR0(1'b0),
2126                 .ADR13(ipmi_bt_input_xfer_read_addr[8]),
2127                 .ADR12(ipmi_bt_input_xfer_read_addr[7]),
2128                 .ADR11(ipmi_bt_input_xfer_read_addr[6]),
2129                 .ADR10(ipmi_bt_input_xfer_read_addr[5]),
2130                 .ADR9(ipmi_bt_input_xfer_read_addr[4]),
2131                 .ADR8(ipmi_bt_input_xfer_read_addr[3]),
2132                 .ADR7(ipmi_bt_input_xfer_read_addr[2]),
2133                 .ADR6(ipmi_bt_input_xfer_read_addr[1]),
2134                 .ADR5(ipmi_bt_input_xfer_read_addr[0]),
2135                 .ADR4(1'b0),
2136                 .ADR3(1'b0),
2137                 .ADR2(1'b0),
2138                 .ADR1(1'b0),
2139                 .ADR0(1'b0),
2140                 .CEW(ipmi_bt_input_xfer_write_wren),
2141                 .CLKW(ipmi_bt_input_xfer_write_clk),
2142                 .CER(1'b1),
2143                 .CLKR(lpc_clock),
2144                 .OCER(1'b1),
2145                 .RST(1'b0)
2146         );
2147
2148         PDPW16KD #(
2149                 .INITVAL_00(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2150                 .INITVAL_01(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2151                 .INITVAL_02(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2152                 .INITVAL_03(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2153                 .INITVAL_04(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2154                 .INITVAL_05(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2155                 .INITVAL_06(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2156                 .INITVAL_07(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2157                 .INITVAL_08(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2158                 .INITVAL_09(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2159                 .INITVAL_0A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2160                 .INITVAL_0B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2161                 .INITVAL_0C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2162                 .INITVAL_0D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2163                 .INITVAL_0E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2164                 .INITVAL_0F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2165                 .INITVAL_10(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2166                 .INITVAL_11(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2167                 .INITVAL_12(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2168                 .INITVAL_13(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2169                 .INITVAL_14(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2170                 .INITVAL_15(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2171                 .INITVAL_16(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2172                 .INITVAL_17(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2173                 .INITVAL_18(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2174                 .INITVAL_19(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2175                 .INITVAL_1A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2176                 .INITVAL_1B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2177                 .INITVAL_1C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2178                 .INITVAL_1D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2179                 .INITVAL_1E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2180                 .INITVAL_1F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2181                 .INITVAL_20(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2182                 .INITVAL_21(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2183                 .INITVAL_22(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2184                 .INITVAL_23(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2185                 .INITVAL_24(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2186                 .INITVAL_25(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2187                 .INITVAL_26(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2188                 .INITVAL_27(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2189                 .INITVAL_28(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2190                 .INITVAL_29(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2191                 .INITVAL_2A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2192                 .INITVAL_2B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2193                 .INITVAL_2C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2194                 .INITVAL_2D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2195                 .INITVAL_2E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2196                 .INITVAL_2F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2197                 .INITVAL_30(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2198                 .INITVAL_31(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2199                 .INITVAL_32(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2200                 .INITVAL_33(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2201                 .INITVAL_34(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2202                 .INITVAL_35(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2203                 .INITVAL_36(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2204                 .INITVAL_37(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2205                 .INITVAL_38(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2206                 .INITVAL_39(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2207                 .INITVAL_3A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2208                 .INITVAL_3B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2209                 .INITVAL_3C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2210                 .INITVAL_3D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2211                 .INITVAL_3E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2212                 .INITVAL_3F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000),
2213                 // Ordinarily this would be 2048 elements deep, 9 bits wide, but Yosys doesn't have support
2214                 // for bit widths other than 36 (https://github.com/YosysHQ/yosys/issues/2143)
2215                 // Since we don't need 2048 (or even 512) elements here, run it in 36 bit data mode with 512 elements
2216                 .DATA_WIDTH_W(36),
2217                 .DATA_WIDTH_R(36)
2218         ) ipmi_bt_cycle_output_xfer_bram(
2219                 .BE3(1'b1),
2220                 .BE2(1'b1),
2221                 .BE1(1'b1),
2222                 .BE0(1'b1),
2223                 .DI7(ipmi_bt_output_xfer_write_data[7]),
2224                 .DI6(ipmi_bt_output_xfer_write_data[6]),
2225                 .DI5(ipmi_bt_output_xfer_write_data[5]),
2226                 .DI4(ipmi_bt_output_xfer_write_data[4]),
2227                 .DI3(ipmi_bt_output_xfer_write_data[3]),
2228                 .DI2(ipmi_bt_output_xfer_write_data[2]),
2229                 .DI1(ipmi_bt_output_xfer_write_data[1]),
2230                 .DI0(ipmi_bt_output_xfer_write_data[0]),
2231                 .CSW2(1'b0),
2232                 .CSW1(1'b0),
2233                 .CSW0(1'b0),
2234                 .ADW8(ipmi_bt_output_xfer_write_addr[8]),
2235                 .ADW7(ipmi_bt_output_xfer_write_addr[7]),
2236                 .ADW6(ipmi_bt_output_xfer_write_addr[6]),
2237                 .ADW5(ipmi_bt_output_xfer_write_addr[5]),
2238                 .ADW4(ipmi_bt_output_xfer_write_addr[4]),
2239                 .ADW3(ipmi_bt_output_xfer_write_addr[3]),
2240                 .ADW2(ipmi_bt_output_xfer_write_addr[2]),
2241                 .ADW1(ipmi_bt_output_xfer_write_addr[1]),
2242                 .ADW0(ipmi_bt_output_xfer_write_addr[0]),
2243                 // NOTE
2244                 // The ECP5 block RAMs operate in a non-intuitive manner.
2245                 // To connect both ports to the same set of memory cells, one port has to be attached
2246                 // 1:1 in address and data lines, while the other is offset (data + 18, address + 5).
2247                 .DO25(ipmi_bt_output_xfer_read_data[7]),
2248                 .DO24(ipmi_bt_output_xfer_read_data[6]),
2249                 .DO23(ipmi_bt_output_xfer_read_data[5]),
2250                 .DO22(ipmi_bt_output_xfer_read_data[4]),
2251                 .DO21(ipmi_bt_output_xfer_read_data[3]),
2252                 .DO20(ipmi_bt_output_xfer_read_data[2]),
2253                 .DO19(ipmi_bt_output_xfer_read_data[1]),
2254                 .DO18(ipmi_bt_output_xfer_read_data[0]),
2255                 .CSR2(1'b0),
2256                 .CSR1(1'b0),
2257                 .CSR0(1'b0),
2258                 .ADR13(ipmi_bt_output_xfer_read_addr[8]),
2259                 .ADR12(ipmi_bt_output_xfer_read_addr[7]),
2260                 .ADR11(ipmi_bt_output_xfer_read_addr[6]),
2261                 .ADR10(ipmi_bt_output_xfer_read_addr[5]),
2262                 .ADR9(ipmi_bt_output_xfer_read_addr[4]),
2263                 .ADR8(ipmi_bt_output_xfer_read_addr[3]),
2264                 .ADR7(ipmi_bt_output_xfer_read_addr[2]),
2265                 .ADR6(ipmi_bt_output_xfer_read_addr[1]),
2266                 .ADR5(ipmi_bt_output_xfer_read_addr[0]),
2267                 .ADR4(1'b0),
2268                 .ADR3(1'b0),
2269                 .ADR2(1'b0),
2270                 .ADR1(1'b0),
2271                 .ADR0(1'b0),
2272                 .CEW(ipmi_bt_output_xfer_write_wren),
2273                 .CLKW(lpc_clock),
2274                 .CER(1'b1),
2275                 .CLKR(ipmi_bt_output_xfer_read_clk),
2276                 .OCER(1'b1),
2277                 .RST(1'b0)
2278         );
2279 endmodule