whitespace cleanup

[nmigen-soc.git] / nmigen_soc / test / test_csr_wishbone.py

diff --git a/nmigen_soc/test/test_csr_wishbone.py b/nmigen_soc/test/test_csr_wishbone.py
index 48dd43f2af6fb57986dead32e7f062b662f6956d..a754d18554f39e6e274efc9cdddc999cac16b80b 100644 (file)
--- a/nmigen_soc/test/test_csr_wishbone.py
+++ b/nmigen_soc/test/test_csr_wishbone.py
@@ -38,7 +38,8 @@ class WishboneCSRBridgeTestCase(unittest.TestCase):
     def test_wrong_csr_bus_data_width(self):
         with self.assertRaisesRegex(ValueError,
                 r"CSR bus data width must be one of 8, 16, 32, 64, not 7"):
-            WishboneCSRBridge(csr_bus=csr.Interface(addr_width=10, data_width=7))
+            WishboneCSRBridge(csr_bus=csr.Interface(addr_width=10,
+                              data_width=7))
 
     def test_narrow(self):
         mux   = csr.Multiplexer(addr_width=10, data_width=8)