import error

[nmigen-soc.git] / nmigen_soc / wishbone / sram.py

diff --git a/nmigen_soc/wishbone/sram.py b/nmigen_soc/wishbone/sram.py
index c5a139df41f1533ea40a63bfff1d78017afd55a9..030ad9073730e6fcb1e97b9b5c6f4b49f1c46936 100644 (file)
--- a/nmigen_soc/wishbone/sram.py
+++ b/nmigen_soc/wishbone/sram.py
@@ -1,7 +1,7 @@
-from nmigen import *
-from nmigen.utils import *
+from nmigen import Elaboratable, Memory, Module
+from nmigen.utils import log2_int
 
-from .bus import Interface
+from nmigen_soc.wishbone.bus import Interface
 
 
 __all__ = ["SRAM"]
@@ -53,7 +53,8 @@ class SRAM(Elaboratable):
         self.memory = memory
         self.read_only = read_only
         if bus is None:
-            bus = Interface(addr_width=log2_int(self.memory.depth, need_pow2=False),
+            bus = Interface(addr_width=log2_int(self.memory.depth,
+                                                need_pow2=False),
                             data_width=self.memory.width,
                             granularity=granularity,
                             features=features,