1 <!-- Instructions here described in PowerISA Version 3.0 B Book 1 -->
3 <!-- Section 3.3.15 Binary Coded Decimal (BCD) Assist Instructions. Page 111 -->
5 <!-- The Binary Coded Decimal Assist instructions operate on Binary Coded Decimal -->
6 <!-- operands (cbcdtd and addg6s) and Decimal Floating-Point operands (cdtbcd) -->
7 <!-- See Chapter 5. for additional information. -->
10 # Convert Declets To Binary Coded Decimal
21 RA[n+8:n+19 ] <- DPD_TO_BCD ( (RS)[n+12:n+21] )
22 RA[n+20:n+31] <- DPD_TO_BCD ( (RS)[n+22:n+31] )
24 Special Registers Altered:
28 # Add and Generate Sixes
38 temp <- (0b0 || RA[4*i:63]) + (0b0 || RB[4*i:63])
40 c <- ([dc[0]]*4 || [dc[1]]*4 || [dc[2]]*4 || [dc[3]]*4 ||
41 [dc[4]]*4 || [dc[5]]*4 || [dc[6]]*4 || [dc[7]]*4 ||
42 [dc[8]]*4 || [dc[9]]*4 || [dc[10]]*4 || [dc[11]]*4 ||
43 [dc[12]]*4 || [dc[13]]*4 || [dc[14]]*4 || [dc[15]]*4)
44 RT <- (¬c) & 0x6666_6666_6666_6666
46 Special Registers Altered:
50 # Convert Binary Coded Decimal To Declets
61 RA[n+12:n+21] <- BCD_TO_DPD ( (RS)[n+8:n+19] )
62 RA[n+22:n+31] <- BCD_TO_DPD ( (RS)[n+20:n+31] )
64 Special Registers Altered:
68 <!-- Checked March 2021 -->