a28e1eef208b1a33f90916887508ceaf0f07732d
1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmutil
.formaltest
import FHDLTestCase
5 from openpower
.decoder
.isa
.caller
import ISACaller
6 from openpower
.decoder
.power_decoder
import (create_pdecode
)
7 from openpower
.decoder
.power_decoder2
import (PowerDecode2
)
8 from openpower
.simulator
.program
import Program
9 from openpower
.decoder
.isa
.caller
import ISACaller
, SVP64State
10 from openpower
.decoder
.selectable_int
import SelectableInt
11 from openpower
.decoder
.orderedset
import OrderedSet
12 from openpower
.decoder
.isa
.all
import ISA
13 from openpower
.decoder
.isa
.test_caller
import Register
, run_tst
14 from copy
import deepcopy
17 class DecoderTestCase(FHDLTestCase
):
19 def _check_regs(self
, sim
, expected_int
, expected_fpr
):
21 self
.assertEqual(sim
.gpr(i
), SelectableInt(expected
[i
], 64))
23 self
.assertEqual(sim
.fpr(i
), SelectableInt(expected_fpr
[i
], 64))
25 def test_fpload(self
):
26 """>>> lst = ["lfsx 1, 0, 0x0008",
29 lst
= ["lfsx 1, 0, 0x0008",
31 initial_mem
= {0x0000: (0x4040266666666666, 8),
32 0x0008: (0xabcdef0187654321, 8),
33 0x0020: (0x1828384822324252, 8),
36 with
Program(lst
, bigendian
=False) as program
:
37 sim
= self
.run_tst_program(program
, initial_mem
=initial_mem
)
38 print("FPR 1", sim
.fpr(1))
39 self
.assertEqual(sim
.fpr(1), SelectableInt(0x4040266666666666, 64))
41 def run_tst_program(self
, prog
, initial_regs
=None,
43 if initial_regs
is None:
44 initial_regs
= [0] * 32
45 simulator
= run_tst(prog
, initial_regs
, mem
=initial_mem
)
53 if __name__
== "__main__":