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[openpower-isa.git] / src / openpower / test / alu / alu_cases.py
1 import random
2 from openpower.test.common import TestAccumulatorBase
3 from openpower.endian import bigendian
4 from openpower.simulator.program import Program
5 from openpower.decoder.selectable_int import SelectableInt
6 from openpower.decoder.power_enums import XER_bits
7 from openpower.decoder.isa.caller import special_sprs
8 from openpower.test.state import ExpectedState
9 import unittest
10
11
12 class ALUTestCase(TestAccumulatorBase):
13
14 def case_1_regression(self):
15 lst = [f"add. 3, 1, 2"]
16 initial_regs = [0] * 32
17 initial_regs[1] = 0xc523e996a8ff6215
18 initial_regs[2] = 0xe1e5b9cc9864c4a8
19 e = ExpectedState(pc=4)
20 e.intregs[1] = 0xc523e996a8ff6215
21 e.intregs[2] = 0xe1e5b9cc9864c4a8
22 e.intregs[3] = 0xa709a363416426bd
23 e.crregs[0] = 0x8
24 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
25
26 def case_2_regression(self):
27 lst = [f"extsw 3, 1"]
28 initial_regs = [0] * 32
29 initial_regs[1] = 0xb6a1fc6c8576af91
30 e = ExpectedState(pc=4)
31 e.intregs[1] = 0xb6a1fc6c8576af91
32 e.intregs[3] = 0xffffffff8576af91
33 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
34
35 lst = [f"subf 3, 1, 2"]
36 initial_regs = [0] * 32
37 initial_regs[1] = 0x3d7f3f7ca24bac7b
38 initial_regs[2] = 0xf6b2ac5e13ee15c2
39 e = ExpectedState(pc=4)
40 e.intregs[1] = 0x3d7f3f7ca24bac7b
41 e.intregs[2] = 0xf6b2ac5e13ee15c2
42 e.intregs[3] = 0xb9336ce171a26947
43 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
44
45 lst = [f"subf 3, 1, 2"]
46 initial_regs = [0] * 32
47 initial_regs[1] = 0x833652d96c7c0058
48 initial_regs[2] = 0x1c27ecff8a086c1a
49 e = ExpectedState(pc=4)
50 e.intregs[1] = 0x833652d96c7c0058
51 e.intregs[2] = 0x1c27ecff8a086c1a
52 e.intregs[3] = 0x98f19a261d8c6bc2
53 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
54
55 lst = [f"extsb 3, 1"]
56 initial_regs = [0] * 32
57 initial_regs[1] = 0x7f9497aaff900ea0
58 e = ExpectedState(pc=4)
59 e.intregs[1] = 0x7f9497aaff900ea0
60 e.intregs[3] = 0xffffffffffffffa0
61 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
62
63 lst = [f"add 3, 1, 2"]
64 initial_regs = [0] * 32
65 initial_regs[1] = 0x2e08ae202742baf8
66 initial_regs[2] = 0x86c43ece9efe5baa
67 e = ExpectedState(pc=4)
68 e.intregs[1] = 0x2e08ae202742baf8
69 e.intregs[2] = 0x86c43ece9efe5baa
70 e.intregs[3] = 0xb4cceceec64116a2
71 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
72
73 def case_rand(self):
74 insns = ["add", "add.", "subf"]
75 for i in range(40):
76 choice = random.choice(insns)
77 lst = [f"{choice} 3, 1, 2"]
78 initial_regs = [0] * 32
79 initial_regs[1] = random.randint(0, (1 << 64)-1)
80 initial_regs[2] = random.randint(0, (1 << 64)-1)
81
82 e = ExpectedState(pc=4)
83 e.intregs[1] = initial_regs[1]
84 e.intregs[2] = initial_regs[2]
85 if choice == "add":
86 result = initial_regs[1] + initial_regs[2]
87 if result < 0:
88 e.intregs[3] = (result + 2**64) & ((2**64)-1)
89 else:
90 e.intregs[3] = result & ((2**64)-1)
91 elif choice == "add.":
92 result = initial_regs[1] + initial_regs[2]
93 if result < 0:
94 e.intregs[3] = (result + 2**64) & ((2**64)-1)
95 else:
96 e.intregs[3] = result & ((2**64)-1)
97 eq = 0
98 gt = 0
99 le = 0
100 if (e.intregs[3] & (1<<63)) != 0:
101 le = 1
102 elif e.intregs[3] == 0:
103 eq = 1
104 else:
105 gt = 1
106 e.crregs[0] = (eq<<1) | (gt<<2) | (le<<3)
107 elif choice == "subf":
108 result = ~initial_regs[1] + initial_regs[2] + 1
109 if result < 0:
110 e.intregs[3] = (result + 2**64) & ((2**64)-1)
111 else:
112 e.intregs[3] = result & ((2**64)-1)
113
114 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
115
116 def case_addme_ca_0(self):
117 insns = ["addme", "addme.", "addmeo", "addmeo."]
118 for choice in insns:
119 lst = [f"{choice} 6, 16"]
120 for value in [0x7ffffffff,
121 0xffff80000]:
122 initial_regs = [0] * 32
123 initial_regs[16] = value
124 initial_sprs = {}
125 xer = SelectableInt(0, 64)
126 xer[XER_bits['CA']] = 0 # input carry is 0 (see test below)
127 initial_sprs[special_sprs['XER']] = xer
128
129 # create expected results. pc should be 4 (one instruction)
130 e = ExpectedState(pc=4)
131 # input value should not be modified
132 e.intregs[16] = value
133 # carry-out should always occur
134 e.ca = 0x3
135 # create output value
136 if value == 0x7ffffffff:
137 e.intregs[6] = 0x7fffffffe
138 else:
139 e.intregs[6] = 0xffff7ffff
140 # CR version needs an expected CR
141 if '.' in choice:
142 e.crregs[0] = 0x4
143 self.add_case(Program(lst, bigendian),
144 initial_regs, initial_sprs,
145 expected=e)
146
147 def case_addme_ca_1(self):
148 insns = ["addme", "addme.", "addmeo", "addmeo."]
149 for choice in insns:
150 lst = [f"{choice} 6, 16"]
151 for value in [0x7ffffffff, # fails, bug #476
152 0xffff80000]:
153 initial_regs = [0] * 32
154 initial_regs[16] = value
155 initial_sprs = {}
156 xer = SelectableInt(0, 64)
157 xer[XER_bits['CA']] = 1 # input carry is 1 (differs from above)
158 initial_sprs[special_sprs['XER']] = xer
159 e = ExpectedState(pc=4)
160 e.intregs[16] = value
161 e.ca = 0x3
162 if value == 0x7ffffffff:
163 e.intregs[6] = 0x7ffffffff
164 else:
165 e.intregs[6] = 0xffff80000
166 if '.' in choice:
167 e.crregs[0] = 0x4
168 self.add_case(Program(lst, bigendian),
169 initial_regs, initial_sprs, expected=e)
170
171 def case_addme_ca_so_4(self):
172 """test of SO being set
173 """
174 lst = ["addmeo. 6, 16"]
175 initial_regs = [0] * 32
176 initial_regs[16] = 0x7fffffffffffffff
177 initial_sprs = {}
178 xer = SelectableInt(0, 64)
179 xer[XER_bits['CA']] = 1
180 initial_sprs[special_sprs['XER']] = xer
181 e = ExpectedState(pc=4)
182 e.intregs[16] = 0x7fffffffffffffff
183 e.intregs[6] = 0x7fffffffffffffff
184 e.ca = 0x3
185 e.crregs[0] = 0x4
186 self.add_case(Program(lst, bigendian),
187 initial_regs, initial_sprs, expected=e)
188
189 def case_addme_ca_so_3(self):
190 """bug where SO does not get passed through to CR0
191 """
192 lst = ["addme. 6, 16"]
193 initial_regs = [0] * 32
194 initial_regs[16] = 0x7ffffffff
195 initial_sprs = {}
196 xer = SelectableInt(0, 64)
197 xer[XER_bits['CA']] = 1
198 xer[XER_bits['SO']] = 1
199 initial_sprs[special_sprs['XER']] = xer
200 e = ExpectedState(pc=4)
201 e.intregs[16] = 0x7ffffffff
202 e.intregs[6] = 0x7ffffffff
203 e.crregs[0] = 0x5
204 e.so = 0x1
205 e.ca = 0x3
206 self.add_case(Program(lst, bigendian),
207 initial_regs, initial_sprs, expected=e)
208
209 def case_addze(self):
210 insns = ["addze", "addze.", "addzeo", "addzeo."]
211 for choice in insns:
212 lst = [f"{choice} 6, 16"]
213 initial_regs = [0] * 32
214 initial_regs[16] = 0x00ff00ff00ff0080
215 e = ExpectedState(pc=4)
216 e.intregs[16] = 0xff00ff00ff0080
217 e.intregs[6] = 0xff00ff00ff0080
218 if '.' in choice:
219 e.crregs[0] = 0x4
220 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
221
222 def case_addis_nonzero_r0_regression(self):
223 lst = [f"addis 3, 0, 1"]
224 print(lst)
225 initial_regs = [0] * 32
226 initial_regs[0] = 5
227 e = ExpectedState(initial_regs, pc=4)
228 e.intregs[3] = 0x10000
229 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
230
231 def case_addis_nonzero_r0(self):
232 for i in range(10):
233 imm = random.randint(-(1 << 15), (1 << 15)-1)
234 lst = [f"addis 3, 0, {imm}"]
235 print(lst)
236 initial_regs = [0] * 32
237 initial_regs[0] = random.randint(0, (1 << 64)-1)
238 e = ExpectedState(pc=4)
239 e.intregs[0] = initial_regs[0]
240 e.intregs[3] = (imm << 16) & ((1<<64)-1)
241 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
242
243 def case_rand_imm(self):
244 insns = ["addi", "addis", "subfic"]
245 for i in range(10):
246 choice = random.choice(insns)
247 imm = random.randint(-(1 << 15), (1 << 15)-1)
248 lst = [f"{choice} 3, 1, {imm}"]
249 print(lst)
250 initial_regs = [0] * 32
251 initial_regs[1] = random.randint(0, (1 << 64)-1)
252
253 e = ExpectedState(pc=4)
254 e.intregs[1] = initial_regs[1]
255 if choice == "addi":
256 result = initial_regs[1] + imm
257 e.intregs[3] = result & ((2**64)-1)
258 elif choice == "addis":
259 result = initial_regs[1] + (imm<<16)
260 if result < 0:
261 e.intregs[3] = (result + 2**64) & ((2**64)-1)
262 else:
263 e.intregs[3] = result & ((2**64)-1)
264 elif choice == "subfic":
265 result = ~initial_regs[1] + imm + 1
266 value = (~initial_regs[1]+2**64) + (imm) + 1
267 if imm < 0:
268 value += 2**64
269 carry_out = value & (1<<64) != 0
270 if imm >= 0:
271 carry_out32 = (((~initial_regs[1]+2**64) & 0xffff_ffff) + \
272 (imm) + 1) & (1<<32)
273 else:
274 carry_out32 = (((~initial_regs[1]+2**64) & 0xffff_ffff) + \
275 (imm+2**32) + 1) & (1<<32)
276 if result < 0:
277 e.intregs[3] = (result + 2**64) & ((2**64)-1)
278 else:
279 e.intregs[3] = result & ((2**64)-1)
280 e.ca = carry_out | (carry_out32>>31)
281
282 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
283
284 def case_0_adde(self):
285 lst = ["adde. 5, 6, 7"]
286 for i in range(10):
287 initial_regs = [0] * 32
288 initial_regs[6] = random.randint(0, (1 << 64)-1)
289 initial_regs[7] = random.randint(0, (1 << 64)-1)
290 initial_sprs = {}
291 xer = SelectableInt(0, 64)
292 xer[XER_bits['CA']] = 1
293 initial_sprs[special_sprs['XER']] = xer
294 # calculate result *including carry* and mask it to 64-bit
295 # (if it overflows, we don't care, because this is not addeo)
296 result = 1 + initial_regs[6] + initial_regs[7]
297 carry_out = result & (1<<64) != 0 # detect 65th bit as carry-out?
298 carry_out32 = ((initial_regs[6] & 0xffff_ffff) + \
299 (initial_regs[7] & 0xffff_ffff)) & (1<<32)
300 result = result & ((1<<64)-1) # round
301 eq = 0
302 gt = 0
303 le = 0
304 if (result & (1<<63)) != 0:
305 le = 1
306 elif result == 0:
307 eq = 1
308 else:
309 gt = 1
310 # now construct the state
311 e = ExpectedState(pc=4)
312 e.intregs[6] = initial_regs[6] # should be same as initial
313 e.intregs[7] = initial_regs[7] # should be same as initial
314 e.intregs[5] = result
315 # carry_out goes into bit 0 of ca, carry_out32 into bit 1
316 e.ca = carry_out | (carry_out32>>31)
317 # eq goes into bit 1 of CR0, gt into bit 2, le into bit 3.
318 # SO goes into bit 0 but overflow doesn't occur here [we hope]
319 e.crregs[0] = (eq<<1) | (gt<<2) | (le<<3)
320
321 self.add_case(Program(lst, bigendian),
322 initial_regs, initial_sprs, expected=e)
323
324 def case_cmp(self):
325 lst = ["subf. 1, 6, 7",
326 "cmp cr2, 1, 6, 7"]
327 initial_regs = [0] * 32
328 initial_regs[6] = 0x10
329 initial_regs[7] = 0x05
330 e = ExpectedState(pc=8)
331 e.intregs[6] = 0x10
332 e.intregs[7] = 0x5
333 e.intregs[1] = 0xfffffffffffffff5
334 e.crregs[0] = 0x8
335 e.crregs[2] = 0x4
336 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
337
338 def case_cmp2(self):
339 lst = ["cmp cr2, 0, 2, 3"]
340 initial_regs = [0] * 32
341 initial_regs[2] = 0xffffffffaaaaaaaa
342 initial_regs[3] = 0x00000000aaaaaaaa
343 e = ExpectedState(pc=4)
344 e.intregs[2] = 0xffffffffaaaaaaaa
345 e.intregs[3] = 0xaaaaaaaa
346 e.crregs[2] = 0x2
347 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
348
349 lst = ["cmp cr2, 0, 4, 5"]
350 initial_regs = [0] * 32
351 initial_regs[4] = 0x00000000aaaaaaaa
352 initial_regs[5] = 0xffffffffaaaaaaaa
353 e = ExpectedState(pc=4)
354 e.intregs[4] = 0xaaaaaaaa
355 e.intregs[5] = 0xffffffffaaaaaaaa
356 e.crregs[2] = 0x2
357 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
358
359 def case_cmp3(self):
360 lst = ["cmp cr2, 1, 2, 3"]
361 initial_regs = [0] * 32
362 initial_regs[2] = 0xffffffffaaaaaaaa
363 initial_regs[3] = 0x00000000aaaaaaaa
364 e = ExpectedState(pc=4)
365 e.intregs[2] = 0xffffffffaaaaaaaa
366 e.intregs[3] = 0xaaaaaaaa
367 e.crregs[2] = 0x8
368 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
369
370 lst = ["cmp cr2, 1, 4, 5"]
371 initial_regs = [0] * 32
372 initial_regs[4] = 0x00000000aaaaaaaa
373 initial_regs[5] = 0xffffffffaaaaaaaa
374 e = ExpectedState(pc=4)
375 e.intregs[4] = 0xaaaaaaaa
376 e.intregs[5] = 0xffffffffaaaaaaaa
377 e.crregs[2] = 0x4
378 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
379
380 def case_cmpl_microwatt_0(self):
381 """microwatt 1.bin:
382 115b8: 40 50 d1 7c .long 0x7cd15040 # cmpl 6, 0, 17, 10
383 register_file.vhdl: Reading GPR 11 000000000001C026
384 register_file.vhdl: Reading GPR 0A FEDF3FFF0001C025
385 cr_file.vhdl: Reading CR 35055050
386 cr_file.vhdl: Writing 35055058 to CR mask 01 35055058
387 """
388
389 lst = ["cmpl 6, 0, 17, 10"]
390 initial_regs = [0] * 32
391 initial_regs[0x11] = 0x1c026
392 initial_regs[0xa] = 0xFEDF3FFF0001C025
393 XER = 0xe00c0000
394 CR = 0x35055050
395
396 e = ExpectedState(pc=4)
397 e.intregs[10] = 0xfedf3fff0001c025
398 e.intregs[17] = 0x1c026
399 e.crregs[0] = 0x3
400 e.crregs[1] = 0x5
401 e.crregs[3] = 0x5
402 e.crregs[4] = 0x5
403 e.crregs[6] = 0x5
404 e.so = 0x1
405 e.ov = 0x3
406 e.ca = 0x3
407
408 self.add_case(Program(lst, bigendian), initial_regs,
409 initial_sprs = {'XER': XER},
410 initial_cr = CR, expected=e)
411
412 def case_cmpl_microwatt_0_disasm(self):
413 """microwatt 1.bin: disassembled version
414 115b8: 40 50 d1 7c .long 0x7cd15040 # cmpl 6, 0, 17, 10
415 register_file.vhdl: Reading GPR 11 000000000001C026
416 register_file.vhdl: Reading GPR 0A FEDF3FFF0001C025
417 cr_file.vhdl: Reading CR 35055050
418 cr_file.vhdl: Writing 35055058 to CR mask 01 35055058
419 """
420
421 dis = ["cmpl 6, 0, 17, 10"]
422 lst = bytes([0x40, 0x50, 0xd1, 0x7c]) # 0x7cd15040
423 initial_regs = [0] * 32
424 initial_regs[0x11] = 0x1c026
425 initial_regs[0xa] = 0xFEDF3FFF0001C025
426 XER = 0xe00c0000
427 CR = 0x35055050
428
429 e = ExpectedState(pc=4)
430 e.intregs[10] = 0xfedf3fff0001c025
431 e.intregs[17] = 0x1c026
432 e.crregs[0] = 0x3
433 e.crregs[1] = 0x5
434 e.crregs[3] = 0x5
435 e.crregs[4] = 0x5
436 e.crregs[6] = 0x5
437 e.so = 0x1
438 e.ov = 0x3
439 e.ca = 0x3
440
441 p = Program(lst, bigendian)
442 p.assembly = '\n'.join(dis)+'\n'
443 self.add_case(p, initial_regs,
444 initial_sprs = {'XER': XER},
445 initial_cr = CR, expected=e)
446
447 def case_cmplw_microwatt_1(self):
448 """microwatt 1.bin:
449 10d94: 40 20 96 7c cmplw cr1,r22,r4
450 gpr: 00000000ffff6dc1 <- r4
451 gpr: 0000000000000000 <- r22
452 """
453
454 lst = ["cmpl 1, 0, 22, 4"]
455 initial_regs = [0] * 32
456 initial_regs[4] = 0xffff6dc1
457 initial_regs[22] = 0
458 XER = 0xe00c0000
459 CR = 0x50759999
460
461 e = ExpectedState(pc=4)
462 e.intregs[4] = 0xffff6dc1
463 e.crregs[0] = 0x5
464 e.crregs[1] = 0x9
465 e.crregs[2] = 0x7
466 e.crregs[3] = 0x5
467 e.crregs[4] = 0x9
468 e.crregs[5] = 0x9
469 e.crregs[6] = 0x9
470 e.crregs[7] = 0x9
471 e.so = 0x1
472 e.ov = 0x3
473 e.ca = 0x3
474
475 self.add_case(Program(lst, bigendian), initial_regs,
476 initial_sprs = {'XER': XER},
477 initial_cr = CR, expected=e)
478
479 def case_cmpli_microwatt(self):
480 """microwatt 1.bin: cmpli
481 123ac: 9c 79 8d 2a cmpli cr5,0,r13,31132
482 gpr: 00000000301fc7a7 <- r13
483 cr : 0000000090215393
484 xer: so 1 ca 0 32 0 ov 0 32 0
485
486 """
487
488 lst = ["cmpli 5, 0, 13, 31132"]
489 initial_regs = [0] * 32
490 initial_regs[13] = 0x301fc7a7
491 XER = 0xe00c0000
492 CR = 0x90215393
493
494 e = ExpectedState(pc=4)
495 e.intregs[13] = 0x301fc7a7
496 e.crregs[0] = 0x9
497 e.crregs[2] = 0x2
498 e.crregs[3] = 0x1
499 e.crregs[4] = 0x5
500 e.crregs[5] = 0x5
501 e.crregs[6] = 0x9
502 e.crregs[7] = 0x3
503 e.so = 0x1
504 e.ov = 0x3
505 e.ca = 0x3
506
507 self.add_case(Program(lst, bigendian), initial_regs,
508 initial_sprs = {'XER': XER},
509 initial_cr = CR, expected=e)
510
511 def case_extsb(self):
512 insns = ["extsb", "extsh", "extsw"]
513 for i in range(10):
514 choice = random.choice(insns)
515 lst = [f"{choice} 3, 1"]
516 print(lst)
517 initial_regs = [0] * 32
518 initial_regs[1] = random.randint(0, (1 << 64)-1)
519
520 e = ExpectedState(pc=4)
521 e.intregs[1] = initial_regs[1]
522 if choice == "extsb":
523 s = ((initial_regs[1] & 0x1000_0000_0000_0080)>>7)&0x1
524 if s == 1:
525 value = 0xffff_ffff_ffff_ff<<8
526 else:
527 value = 0x0
528 e.intregs[3] = value | (initial_regs[1] & 0xff)
529 elif choice == "extsh":
530 s = ((initial_regs[1] & 0x1000_0000_0000_8000)>>15)&0x1
531 if s == 1:
532 value = 0xffff_ffff_ffff<<16
533 else:
534 value = 0x0
535 e.intregs[3] = value | (initial_regs[1] & 0xffff)
536 else:
537 s = ((initial_regs[1] & 0x1000_0000_8000_0000)>>31)&0x1
538 if s == 1:
539 value = 0xffff_ffff<<32
540 else:
541 value = 0x0
542 e.intregs[3] = value | (initial_regs[1] & 0xffff_ffff)
543
544 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
545
546 def case_cmpeqb(self):
547 lst = ["cmpeqb cr1, 1, 2"]
548 for i in range(20):
549 initial_regs = [0] * 32
550 initial_regs[1] = i
551 initial_regs[2] = 0x0001030507090b0f
552
553 e = ExpectedState(pc=4)
554 e.intregs[1] = i
555 e.intregs[2] = 0x1030507090b0f
556 matlst = [ 0x00, 0x01, 0x03, 0x05, 0x07, 0x09, 0x0b, 0x0f ]
557 for j in matlst:
558 if j == i:
559 e.crregs[1] = 0x4
560
561 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
562