24608e471c968cc7caf6e6b72b2966886597d2d3
1 from openpower
.test
.common
import TestAccumulatorBase
, skip_case
2 from openpower
.sv
.trans
.svp64
import SVP64Asm
3 from openpower
.test
.state
import ExpectedState
4 from openpower
.simulator
.program
import Program
5 from openpower
.decoder
.isa
.caller
import SVP64State
7 _SHIFT_TEST_RANGE
= list(range(-64, 128, 16)) + [1, 63]
10 class BigIntCases(TestAccumulatorBase
):
11 def case_maddedu(self
):
12 lst
= list(SVP64Asm(["maddedu 3,5,6,7"]))
14 gprs
[5] = 0x123456789ABCDEF
15 gprs
[6] = 0xFEDCBA9876543210
16 gprs
[7] = 0x02468ACE13579BDF
17 e
= ExpectedState(pc
=4, int_regs
=gprs
)
18 e
.intregs
[3] = (gprs
[5] * gprs
[6] + gprs
[7]) % 2 ** 64
19 e
.intregs
[7] = (gprs
[5] * gprs
[6] + gprs
[7]) >> 64
20 self
.add_case(Program(lst
, False), gprs
, expected
=e
)
22 def case_divmod2du(self
):
23 lst
= list(SVP64Asm(["divmod2du 3,5,6,7"]))
25 gprs
[5] = 0x123456789ABCDEF
26 gprs
[6] = 0xFEDCBA9876543210
27 gprs
[7] = 0x02468ACE13579BDF
28 e
= ExpectedState(pc
=4, int_regs
=gprs
)
29 v
= gprs
[5] |
(gprs
[7] << 64)
30 e
.intregs
[3] = v
// gprs
[6]
31 e
.intregs
[7] = v
% gprs
[6]
32 self
.add_case(Program(lst
, False), gprs
, expected
=e
)
34 # FIXME: test more divmod2du special cases
37 prog
= Program(list(SVP64Asm(["dsld 3,4,5,6"])), False)
38 for sh
in _SHIFT_TEST_RANGE
:
39 with self
.subTest(sh
=sh
):
41 gprs
[6] = 0x123456789ABCDEF
42 gprs
[4] = 0xFEDCBA9876543210
43 gprs
[5] = sh
% 2 ** 64
44 e
= ExpectedState(pc
=4, int_regs
=gprs
)
49 e
.intregs
[3] = v
% 2 ** 64
50 e
.intregs
[6] = (v
>> 64) % 2 ** 64
51 self
.add_case(prog
, gprs
, expected
=e
)
54 prog
= Program(list(SVP64Asm(["dsrd 3,4,5,6"])), False)
55 for sh
in _SHIFT_TEST_RANGE
:
56 with self
.subTest(sh
=sh
):
58 gprs
[6] = 0x123456789ABCDEF
59 gprs
[4] = 0xFEDCBA9876543210
60 gprs
[5] = sh
% 2 ** 64
61 e
= ExpectedState(pc
=4, int_regs
=gprs
)
64 mask
= ~
((2 ** 64 - 1) >> (sh
%64))
66 print ("case_dsrd0", hex(mask
), sh
, hex(v
))
67 e
.intregs
[3] = v
% 2 ** 64
68 e
.intregs
[6] = (v
>> 64) % 2 ** 64
69 self
.add_case(prog
, gprs
, expected
=e
)
72 class SVP64BigIntCases(TestAccumulatorBase
):
73 def case_sv_bigint_add(self
):
74 """performs a carry-rollover-vector-add aka "big integer vector add"
75 this is remarkably simple, each sv.adde uses and produces a CA which
76 goes into the next sv.adde. arbitrary size is possible (1024+) as
77 is looping using the CA bit from one sv.adde on another batch to do
78 unlimited-size biginteger add.
80 r19/r18: 0x0000_0000_0000_0001 0xffff_ffff_ffff_ffff +
81 r21/r20: 0x8000_0000_0000_0000 0x0000_0000_0000_0001 =
82 r17/r16: 0x8000_0000_0000_0002 0x0000_0000_0000_0000
84 prog
= Program(list(SVP64Asm(["sv.adde *16, *18, *20"])), False)
86 gprs
[18] = 0xffff_ffff_ffff_ffff
87 gprs
[19] = 0x0000_0000_0000_0001
88 gprs
[20] = 0x0000_0000_0000_0001
89 gprs
[21] = 0x8000_0000_0000_0000
90 svstate
= SVP64State()
93 e
= ExpectedState(pc
=8, int_regs
=gprs
)
94 e
.intregs
[16] = 0x0000_0000_0000_0000
95 e
.intregs
[17] = 0x8000_0000_0000_0002
96 self
.add_case(prog
, gprs
, expected
=e
, initial_svstate
=svstate
)
98 def case_sv_bigint_shift_right_by_scalar(self
):
99 """performs a bigint shift-right by scalar.
101 r0 starts off (as the carry-in) at 0x9000_0000_0000_0000
104 0x0000_0000_5000_0002 0x8000_8000_8000_8001 0xffff_ffff_ffff_ffff >> 4
105 0x0000_0000_0500_0000 0x2800_0800_0800_0800 0x1fff_ffff_ffff_ffff
107 with the 4-bit part that drops out of the 4 LSBs of r16 ending up
110 prog
= Program(list(SVP64Asm(["sv.dsrd/mrr *16,*16,4,0"])), False)
112 gprs
[0] = 0x9000_0000_0000_0000
113 gprs
[16] = 0xffff_ffff_ffff_ffff
114 gprs
[17] = 0x8000_8000_8000_8001
115 gprs
[18] = 0x0000_0000_5000_0002
117 svstate
= SVP64State()
120 e
= ExpectedState(pc
=8, int_regs
=gprs
)
121 e
.intregs
[0] = 0xf000_0000_0000_0000 # remainder (shifted out of 16)
122 e
.intregs
[16] = 0x1fff_ffff_ffff_ffff
123 e
.intregs
[17] = 0x2800_0800_0800_0800
124 e
.intregs
[18] = 0x9000_0000_0500_0000 # initial r0 into top
125 self
.add_case(prog
, gprs
, expected
=e
, initial_svstate
=svstate
)
127 def case_sv_bigint_shift_left_by_scalar(self
):
128 """performs a bigint shift-left by scalar.
130 because the result is moved down by one register there is no need
133 r14 starts off as the carry-in: 0xa000_0000_0000_0000
136 0x9000_0000_0001_0002 0x3fff_ffff_ffff_ffff 0x4000_0000_0000_0001 << 4
138 0x0000_0000_0010_0023 0xffff_ffff_ffff_fff4 0x0000_0000_0000_0010
140 with the top 4 bits of r18 being pushed into the LSBs of r14
142 prog
= Program(list(SVP64Asm(["sv.dsld *16,*16,4,14"])), False)
144 gprs
[14] = 0x0000_0000_0000_000a
145 gprs
[16] = 0x4000_0000_0000_0001
146 gprs
[17] = 0x3fff_ffff_ffff_ffff
147 gprs
[18] = 0x9000_0000_0001_0002
149 svstate
= SVP64State()
152 e
= ExpectedState(pc
=8, int_regs
=gprs
)
154 e
.intregs
[16] = 0x0000_0000_0000_001a
155 e
.intregs
[17] = 0xffff_ffff_ffff_fff4
156 e
.intregs
[18] = 0x0000_0000_0010_0023
157 self
.add_case(prog
, gprs
, expected
=e
, initial_svstate
=svstate
)
159 def case_sv_bigint_mul_by_scalar(self
):
160 """performs a carry-rollover-vector-mul-with-add with a scalar,
161 using "RC" as a 64-bit carry in/out. matched with the
165 0x1234_0000_5678_0000 0x9ABC_0000_DEF0_0000 0x1357_0000_9BDF_0000 *
166 r3 (scalar factor) 0x1_0001 +
167 r4 (carry in) 0xFEDC =
169 0x1234_5678_5678_9ABC 0x9ABC_DEF0_DEF0_1357 0x1357_9BDF_9BDF_FEDC
170 r4 (carry out) 0x1234
172 prog
= Program(list(SVP64Asm(["sv.maddedu *16,*16,3,4"])), False)
174 gprs
[16] = 0x1357_0000_9BDF_0000 # vector...
175 gprs
[17] = 0x9ABC_0000_DEF0_0000 # ...
176 gprs
[18] = 0x1234_0000_5678_0000 # ... input
177 gprs
[3] = 0x1_0001 # scalar multiplier
178 gprs
[4] = 0xFEDC # 64-bit carry-in
179 svstate
= SVP64State()
182 e
= ExpectedState(pc
=8, int_regs
=gprs
)
183 e
.intregs
[16] = 0x1357_9BDF_9BDF_FEDC # vector...
184 e
.intregs
[17] = 0x9ABC_DEF0_DEF0_1357 # ...
185 e
.intregs
[18] = 0x1234_5678_5678_9ABC # ... result
186 e
.intregs
[4] = 0x1234 # 64-bit carry-out
187 self
.add_case(prog
, gprs
, expected
=e
, initial_svstate
=svstate
)
189 def case_sv_bigint_scalar_maddedu(self
):
190 prog
= Program(list(SVP64Asm(["sv.maddedu 6,5,3,4"])), False)
192 gprs
[5] = 0x1357_0000_9BDF_0000 # scalar input
193 gprs
[3] = 0x1_0001 # scalar multiplier
194 gprs
[4] = 0xFEDC # 64-bit carry-in
195 svstate
= SVP64State()
196 svstate
.vl
= 16 # detect writing to RT+MAXVL or RT+1 rather than RC
198 e
= ExpectedState(pc
=8, int_regs
=gprs
)
199 e
.intregs
[6] = 0x1357_9BDF_9BDF_FEDC # scalar output
200 e
.intregs
[4] = 0x1357 # 64-bit carry-out
201 self
.add_case(prog
, gprs
, expected
=e
, initial_svstate
=svstate
)
203 def case_sv_bigint_div_by_scalar(self
):
204 """performs a carry-rollover-vector-divmod with a scalar,
205 using "RC" as a 64-bit carry. matched with the sv.maddedu
206 above it is effectively the scalar-vector inverse
209 0x1234_5678_5678_9ABC 0x9ABC_DEF0_DEF0_1357 0x1357_9BDF_9BDF_FEDC /
210 r3 (scalar factor) 0x1_0001 +
211 r4 (carry in at top-end) 0x1234 << 192 =
213 0x1234_0000_5678_0000 0x9ABC_0000_DEF0_0000 0x1357_0000_9BDF_0000 *
214 r4 (carry out i.e. scalar remainder) 0xFEDC
216 prog
= Program(list(SVP64Asm(["sv.divmod2du/mrr *16,*16,3,4"])), False)
218 gprs
[16] = 0x1357_9BDF_9BDF_FEDC # vector...
219 gprs
[17] = 0x9ABC_DEF0_DEF0_1357 # ...
220 gprs
[18] = 0x1234_5678_5678_9ABC # ... input
221 gprs
[3] = 0x1_0001 # scalar multiplier
222 gprs
[4] = 0x1234 # 64-bit carry-in
223 svstate
= SVP64State()
226 e
= ExpectedState(pc
=8, int_regs
=gprs
)
227 e
.intregs
[16] = 0x1357_0000_9BDF_0000 # vector...
228 e
.intregs
[17] = 0x9ABC_0000_DEF0_0000 # ...
229 e
.intregs
[18] = 0x1234_0000_5678_0000 # ... result
230 e
.intregs
[4] = 0xFEDC # 64-bit carry-out
231 self
.add_case(prog
, gprs
, expected
=e
, initial_svstate
=svstate
)