return SelectableInt(exts(value.value, value.bits) & ((1 << 128)-1), 128)
+def copy_assign_rhs(inp):
+ """ implicitly added function call to all assignment RHSes.
+ This copies the passed-in value so later assignments to parts of the
+ LHS don't modify the RHS if it's a SelectableInt.
+
+ Example:
+ ```
+ # this needs to copy the SelectableInt instance in RA
+ # not just assign a reference to it to A
+ A <- RA
+ A[0] <- 1 # if the copy wasn't performed, we just modified RA too!
+ ```
+ """
+ if isinstance(inp, (str, int)):
+ return inp
+ if isinstance(inp, (SelectableInt, FieldSelectableInt)):
+ return SelectableInt(inp)
+ if isinstance(inp, BFPState):
+ return BFPState(inp)
+ if isinstance(inp, SelectableMSB0Fraction):
+ return SelectableMSB0Fraction(inp)
+ if isinstance(inp, tuple):
+ return tuple(map(copy_assign_rhs, inp))
+ if isinstance(inp, dict):
+ return {copy_assign_rhs(k): copy_assign_rhs(v) for k, v in inp.items()}
+ raise TypeError("tried to assign an unsupported type in pseudo-code",
+ repr(type(inp)))
+
+
# signed version of MUL
def MULS(a, b):
if isinstance(b, int):
self.read_regs.add(toname)
if name and name in self.gprs:
self.write_regs.add(name) # add to list of regs to write
- p[0] = self.Assign(autoassign, name, p[1], p[3], iea_mode,
+
+ # copy rhs -- see openpower.decoder.helpers.copy_assign_rhs()'s
+ # documentation for why we need this
+ copy_fn = ast.Name("copy_assign_rhs", ast.Load())
+ rhs = ast.Call(copy_fn, (p[3],), [])
+ p[0] = self.Assign(autoassign, name, p[1], rhs, iea_mode,
p.slice[2])
if name:
self.declared_vars.add(name)
from openpower.decoder.isa.caller import inject
from openpower.decoder.helpers import (ISACallerHelper,
ne, eq, gt, ge, lt, le, ltu, gtu, length,
- trunc_divs, trunc_rems,
+ trunc_divs, trunc_rems, copy_assign_rhs,
)
from openpower.decoder.selectable_int import SelectableInt
from openpower.decoder.selectable_int import selectconcat as concat
from openpower.decoder.isa.caller import inject, instruction_info
from openpower.decoder.helpers import (
ne, eq, gt, ge, lt, le, ltu, gtu, length,
- RANGE,
+ RANGE, copy_assign_rhs,
ISACallerHelper,
)
from openpower.decoder.selectable_int import SelectableInt
class TrapTestCase(TestAccumulatorBase):
-
def case_1_kaivb(self):
# https://bugs.libre-soc.org/show_bug.cgi?id=859
lst = ["mtspr 850, 1", # KAIVB
msr = 0xa000000000000003
self.add_case(Program(lst, bigendian),
initial_regs, initial_sprs,
- initial_msr=msr)
+ initial_msr=msr)
def case_2_kaivb_test(self):
# https://bugs.libre-soc.org/show_bug.cgi?id=859
"tbegin.", # deliberately use illegal instruction
]
initial_regs = [0] * 32
- initial_regs[1] = 1<<13
+ initial_regs[1] = 1 << 13
initial_sprs = {'KAIVB': 0x12345678,
}
msr = 0xa000000000000003
e = ExpectedState(pc=0x2700)
- e.intregs[1] = 1<<13
- e.msr = 0xa000000000000003 # TODO, not actually checked
+ e.intregs[1] = 1 << 13
+ e.sprs['SRR0'] = 0x4
+ e.sprs['SRR1'] = 0xa000000000080003
+ e.sprs['KAIVB'] = 0x2000
+ e.msr = 0xa000000000000001
self.add_case(Program(lst, bigendian),
initial_regs, initial_sprs,
- initial_msr=msr,
- expected=e)
+ initial_msr=msr,
+ expected=e)
def case_0_hrfid(self):
lst = ["hrfid"]
lst = ["sc 0"]
initial_regs = [0] * 32
initial_regs[1] = 1
- initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678} # to overwrite
+ initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678} # to overwrite
# expected results: PC should be at 0xc00 (sc address)
e = ExpectedState(pc=0xc00)
e.intregs[1] = 1
e.sprs['SRR0'] = 4 # PC to return to: CIA+4
- e.sprs['SRR1'] = 0x9000000000022903 # MSR to restore after sc return
+ e.sprs['SRR1'] = 0x9000000000022903 # MSR to restore after sc return
e.msr = 0x9000000000000001 # MSR changed to this by sc/trap
self.add_case(Program(lst, bigendian),
initial_regs, initial_sprs,
initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0xb000000000001033}
e = ExpectedState(pc=0x700)
e.intregs[1] = 1
- e.msr = 0xb000000000001033 # TODO, not actually checked
+ e.msr = 0xb000000000001033 # TODO, not actually checked
self.add_case(Program(lst, bigendian),
initial_regs, initial_sprs,
- initial_msr=0xa000000000000003,
- expected=e)
+ initial_msr=0xa000000000000003,
+ expected=e)
def case_0_trap_eq_imm(self):
insns = ["twi", "tdi"]
initial_regs = [0] * 32
initial_regs[1] = 0xb000000000001033
self.add_case(Program(lst, bigendian), initial_regs,
- initial_msr=0xa000000000000003)
+ initial_msr=0xa000000000000003)
def case_4_mtmsrd_0(self):
lst = ["mtmsrd 1,0"]
"mtmsr 1,1"] # should not get executed
initial_regs = [0] * 32
self.add_case(Program(lst, bigendian), initial_regs)
-
projects / openpower-isa.git / commitdiff