remove dead code, sv.svstep and sv.fcoss are now handled by CUSTOM_INSNS

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index 53bc77287d7023250bd18a7a850096472674535c..0c3e3f876420a5c05d214b15c97ff68730c47048 100644 (file)
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -1340,27 +1340,6 @@ class SVP64Asm:
             if rc:
                 opcode |= 1  # Rc, bit 31.
             yield ".long 0x%x" % opcode
-        # sigh have to do svstep here manually for now...
-        elif v30b_op in ["svstep", "svstep."]:
-            insn = 22 << (31-5)          # opcode 22, bits 0-5
-            insn |= int(v30b_newfields[0]) << (31-10)  # RT       , bits 6-10
-            insn |= int(v30b_newfields[1]) << (31-22)  # SVi      , bits 16-22
-            insn |= int(v30b_newfields[2]) << (31-25)  # vf       , bit  25
-            insn |= 0b10011 << (31-30)  # XO       , bits 26..30
-            if opcode == 'svstep.':
-                insn |= 1 << (31-31)     # Rc=1     , bit 31
-            log("svstep", bin(insn))
-            yield ".long 0x%x" % insn
-        # argh, sv.fcoss etc. need to be done manually
-        elif v30b_op in ["fcoss", "fcoss."]:
-            insn = 59 << (31-5)  # opcode 59, bits 0-5
-            insn |= int(v30b_newfields[0]) << (31-10)  # RT       , bits 6-10
-            insn |= int(v30b_newfields[1]) << (31-20)  # RB       , bits 16-20
-            insn |= 0b1000101110 << (31-30)  # XO       , bits 21..30
-            if opcode == 'fcoss.':
-                insn |= 1 << (31-31)     # Rc=1     , bit 31
-            log("fcoss", bin(insn))
-            yield ".long 0x%x" % insn
         else:
             if not v30b_op.endswith('.'):
                 v30b_op += rc