move round_float to separate file
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 15 May 2021 23:08:34 +0000 (00:08 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 15 May 2021 23:08:34 +0000 (00:08 +0100)
openpower/isafunctions/fpfromint.mdwn
openpower/isafunctions/roundfloat.mdwn [new file with mode: 0644]

index 3ed1bed33fabbfc9334fed8d97b2e1b7f1182b2d..c182bfd51a9cdb03b69265b07b3e3191ab85c0d4 100644 (file)
@@ -5,43 +5,6 @@ Convert From Integer instructions.
 
 <!-- Power ISA Book I Version 3.0B Section A.3 page 782 -->
 
 
 <!-- Power ISA Book I Version 3.0B Section A.3 page 782 -->
 
-    def Round_Float( tgt_precision, sign, exp, frac, round_mode ):
-       inc <- 0
-       if tgt_precision = "single-precision" then
-           lsb <- frac[23]
-           gbit <- frac[24]
-           rbit <- frac[25]
-           xbit <- frac[26:63] > 0
-        else # tgt_precision = "double-precision"
-            lsb  <= frac[52]
-            gbit <= frac[53]
-            rbit <= frac[54]
-            xbit <= frac[55:63] > 0
-
-        if round_mode  = 0b00  then           # Round to Nearest
-            if lsb = 1 and gbit = 1              then inc <- 1
-            if lsb = 0 and gbit = 1 and rbit = 1 then inc <- 1
-            if lsb = 0 and gbit = 1 and xbit = 1 then inc <- 1
-        end
-        if round_mode  = 0b10  then           # Round toward + Infinity
-            if sign = 0 and gbit = 1 then inc <-1
-            if sign = 0 and rbit = 1 then inc <-1
-            if sign = 0 and xbit = 1 then inc <-1
-        end
-        if round_mode  = 0b11  then           # Round toward - Infinity
-            if sign = 1 and gbit = 1 then inc <-1
-            if sign = 1 and rbit = 1 then inc <-1
-            if sign = 1 and xbit = 1 then inc <-1
-        end
-        if tgt_precision = "single-precision" then
-            frac[0:23] <- frac[0:23] + inc
-        else # tgt_precision = "double-precision"
-            frac[0:52] <- frac[0:52] + inc
-        if carry_out = 1 then exp <- exp + 1
-        FPSCR[FR] <- inc
-        FPSCR[FI] <- gbit | rbit | xbit
-        FPSCR[XX] <- FPSCR[XX] | FPSCR[FI]
-
     def INT2FP(FR, cvt, RN):
         if cvt = "sint2double" then
             tgt_precision = "double-precision"
     def INT2FP(FR, cvt, RN):
         if cvt = "sint2double" then
             tgt_precision = "double-precision"
diff --git a/openpower/isafunctions/roundfloat.mdwn b/openpower/isafunctions/roundfloat.mdwn
new file mode 100644 (file)
index 0000000..229e9bb
--- /dev/null
@@ -0,0 +1,41 @@
+# A.3 Round to Float conversion
+
+<!-- Power ISA Book I Version 3.0B Section A.3 page 782 -->
+
+    def Round_Float( tgt_precision, sign, exp, frac, round_mode ):
+       inc <- 0
+       if tgt_precision = "single-precision" then
+           lsb <- frac[23]
+           gbit <- frac[24]
+           rbit <- frac[25]
+           xbit <- frac[26:63] > 0
+        else # tgt_precision = "double-precision"
+            lsb  <= frac[52]
+            gbit <= frac[53]
+            rbit <= frac[54]
+            xbit <= frac[55:63] > 0
+
+        if round_mode  = 0b00  then           # Round to Nearest
+            if lsb = 1 and gbit = 1              then inc <- 1
+            if lsb = 0 and gbit = 1 and rbit = 1 then inc <- 1
+            if lsb = 0 and gbit = 1 and xbit = 1 then inc <- 1
+        end
+        if round_mode  = 0b10  then           # Round toward + Infinity
+            if sign = 0 and gbit = 1 then inc <-1
+            if sign = 0 and rbit = 1 then inc <-1
+            if sign = 0 and xbit = 1 then inc <-1
+        end
+        if round_mode  = 0b11  then           # Round toward - Infinity
+            if sign = 1 and gbit = 1 then inc <-1
+            if sign = 1 and rbit = 1 then inc <-1
+            if sign = 1 and xbit = 1 then inc <-1
+        end
+        if tgt_precision = "single-precision" then
+            frac[0:23] <- frac[0:23] + inc
+        else # tgt_precision = "double-precision"
+            frac[0:52] <- frac[0:52] + inc
+        if carry_out = 1 then exp <- exp + 1
+        FPSCR[FR] <- inc
+        FPSCR[FI] <- gbit | rbit | xbit
+        FPSCR[XX] <- FPSCR[XX] | FPSCR[FI]
+