rename divrem2du->divmod2du for consistency with PowerISA mod* instructions

diff --git a/openpower/isa/svfixedarith.mdwn b/openpower/isa/svfixedarith.mdwn
index 18e701784961979d4363974755b4c26087aec4f9..a799236446a7943f551e776a6c293d0756a7f0a7 100644 (file)
--- a/openpower/isa/svfixedarith.mdwn
+++ b/openpower/isa/svfixedarith.mdwn
@@ -22,7 +22,7 @@ Special Registers Altered:
 
 VA-Form
 
-* divrem2du   RT,RA,RB,RC
+* divmod2du   RT,RA,RB,RC
 
 Pseudo-code:
 

diff --git a/openpower/isatables/RM-1P-3S1D.csv b/openpower/isatables/RM-1P-3S1D.csv
index 86f67d6eddd70f82bd0f999949258dfff2b7e33f..e3e59de1d67a8330852a2636efd7262fd16934b0 100644 (file)
--- a/openpower/isatables/RM-1P-3S1D.csv
+++ b/openpower/isatables/RM-1P-3S1D.csv
@@ -35,7 +35,7 @@ maddhd,NORMAL,,1P,EXTRA2,NO,d:RT,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,0,0
 maddhdu,NORMAL,,1P,EXTRA2,NO,d:RT,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,0,0
 madded,NORMAL,,1P,EXTRA2,NO,d:RT,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,0,0
 maddld,NORMAL,,1P,EXTRA2,NO,d:RT,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,0,0
-divrem2du,NORMAL,,1P,EXTRA2,NO,d:RT,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,0,0
+divmod2du,NORMAL,,1P,EXTRA2,NO,d:RT,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,0,0
 absdacs,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RT,RA,RB,RT,RT,0,CR0,0
 absdacu,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RT,RA,RB,RT,RT,0,CR0,0
 pcdec,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,CR0,0

diff --git a/openpower/isatables/minor_4.csv b/openpower/isatables/minor_4.csv
index 80dd9f8bdf2b53c30d23cf57664ffabc8bf75957..57fd539699c94687fa9333cf4007126ded450d7c 100644 (file)
--- a/openpower/isatables/minor_4.csv
+++ b/openpower/isatables/minor_4.csv
@@ -5,6 +5,6 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 49,ALU,OP_MADDHDU,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddhdu,VA,,,
 50,ALU,OP_MADDED,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,madded,VA,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 51,ALU,OP_MADDLD,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddld,VA,,,
-52,ALU,OP_DIVREM2DU,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,divrem2du,VA,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+52,ALU,OP_DIVMOD2DU,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,divmod2du,VA,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 56,ALU,OP_PCDEC,RA,RB,RC,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,ONE,0,0,pcdec,VA2,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 57,ALU,OP_PCDEC,RA,RB,RC,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,ONE,0,0,pcdec,VA2,,1,unofficial until submitted and approved/renumbered by the opf isa wg

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index fe1edd9da87e30a95f2757dd4badf5ca3453ab81..34c776280b3e04b07f15f1dbabbea1e36424d9a3 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1588,7 +1588,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
                        'svshape', 'svshape2',
                        'grev', 'ternlogi', 'bmask', 'cprop',
                        'absdu', 'absds', 'absdacs', 'absdacu', 'avgadd',
-                       'fmvis', 'fishmv', 'pcdec', "madded", "divrem2du",
+                       'fmvis', 'fishmv', 'pcdec', "madded", "divmod2du",
                        "dsld", "dsrd",
                        ]:
             illegal = False

diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py
index ff95728b64f21247985d9b0c87939cfe19da860f..6d9e2a7a5f6d4f4ef97034cb12e7d4a7eebb3af2 100644 (file)
--- a/src/openpower/decoder/power_decoder2.py
+++ b/src/openpower/decoder/power_decoder2.py
@@ -1038,7 +1038,7 @@ class PowerDecodeSubset(Elaboratable):
             with m.If((major == 4) & xo6.matches(
                     '11100-',  # pcdec
                     '110010',  # madded
-                    '110100',  # divrem2du
+                    '110100',  # divmod2du
                 )):
                 comb += self.implicit_rs.eq(1)
 

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index 9ec62380c11246b402cffffaae7d13f2ec4567cf..7eb310ff5c6f88e73812e832d7335be8dbe81f55 100644 (file)
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -508,7 +508,7 @@ _insns = [
     "dcbf", "dcbst", "dcbt", "dcbtst", "dcbz",
     "divd", "divde", "divdeo", "divdeu",
     "divdeuo", "divdo", "divdu", "divduo",
-    "divrem2du",
+    "divmod2du",
     "divw", "divwe", "divweo",
     "divweu", "divweuo", "divwo", "divwu", "divwuo",
     "dsld", "dsrd",
@@ -699,7 +699,7 @@ class MicrOp(Enum):
     OP_FISHMV = 97
     OP_PCDEC = 98
     OP_MADDED = 99
-    OP_DIVREM2DU = 100
+    OP_DIVMOD2DU = 100
     OP_DSHL = 101
     OP_DSHR = 102
 

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index e1c7d14508ed949bdfc91a9b2d42aff1947ca33b..209cb08bb7e37ddec629b6a1c75b14a777af0d5a 100644 (file)
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -588,7 +588,7 @@ def pcdec(fields):
 
 @_custom_insns(
     _insn("madded", XO=50),
-    _insn("divrem2du", XO=52),
+    _insn("divmod2du", XO=52),
 )
 def va_form(fields, XO):
     # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG

diff --git a/src/openpower/test/bigint/bigint_cases.py b/src/openpower/test/bigint/bigint_cases.py
index b847ba09aeffe8da39431fcd54684529ac9d1aba..622bbf373581c9fd95439fa06c5232cab8c15c83 100644 (file)
--- a/src/openpower/test/bigint/bigint_cases.py
+++ b/src/openpower/test/bigint/bigint_cases.py
@@ -18,8 +18,8 @@ class BigIntCases(TestAccumulatorBase):
         e.intregs[4] = (gprs[5] * gprs[6] + gprs[7]) >> 64
         self.add_case(Program(lst, False), gprs, expected=e)
 
-    def case_divrem2du(self):
-        lst = list(SVP64Asm(["divrem2du 3,5,6,7"]))
+    def case_divmod2du(self):
+        lst = list(SVP64Asm(["divmod2du 3,5,6,7"]))
         gprs = [0] * 32
         gprs[5] = 0x123456789ABCDEF
         gprs[6] = 0xFEDCBA9876543210
@@ -30,7 +30,7 @@ class BigIntCases(TestAccumulatorBase):
         e.intregs[4] = v % gprs[6]
         self.add_case(Program(lst, False), gprs, expected=e)
 
-    # FIXME: test more divrem2du special cases
+    # FIXME: test more divmod2du special cases
 
     def case_dsld0(self):
         prog = Program(list(SVP64Asm(["dsld 3,4,5,0"])), False)