openpower-isa.git
2023-06-10 Jacob Lifshaysilence log by default just in fmv/fcvt and utf-8 tests pytest7
2023-06-10 Jacob LifshayRevert "disable fmv / fcvt unit tests as there are...
2023-06-10 Jacob LifshayRevert "disable fmv-fcvt tests entirely"
2023-06-10 Jacob LifshayRevert "far too much memory (58 GB) being used by these...
2023-06-10 Jacob Lifshayuse pytest-output-to-files plugin with pytest==7.3...
2023-06-09 Dmitry Selyutininsndb/core: support class walking
2023-06-09 Dmitry Selyutininsndb: rename subnodes into walk
2023-06-09 Dmitry Selyutininsndb/core: introduce Records type
2023-06-09 Dmitry Selyutininsndb/core: switch dataclasses to Dataclass type
2023-06-09 Dmitry Selyutininsndb/core: introduce Path type
2023-06-08 Dmitry Selyutininsndb/core: inroduce String type
2023-06-08 Dmitry Selyutininsndb: decouple visitors and walking
2023-06-07 Dmitry Selyutininsndb: decouple visitors and walking
2023-06-07 Dmitry Selyutininsndb: refactor visitors (again)
2023-06-07 Luke Kenneth... comment out debug log
2023-06-07 Luke Kenneth... remove print log
2023-06-07 Dmitry Selyutininsndb: refactor visitors
2023-06-07 Dmitry Selyutininsn/core: rename extra-related classes
2023-06-05 Dmitry Selyutinpower_enums: distinguish all reg types
2023-06-04 Dmitry Selyutininsndb/db: refactor visitors
2023-06-04 Dmitry Selyutininsn/core: introduce visitable extra
2023-06-04 Dmitry Selyutininsndb/db: support operand spans
2023-06-04 Dmitry Selyutininsn/db: restrict extras command with SVP64 instructions
2023-06-04 Dmitry Selyutinpower_enums: simplify sel type string conversion
2023-06-04 Dmitry Selyutinpower_enums: simplify extra idx string conversion
2023-06-04 Dmitry Selyutinpower_enums: align reg pairs
2023-06-04 Dmitry Selyutinpower_enums: simplify reg string conversion
2023-06-04 Dmitry Selyutinpower_enums: simplify selectors string conversion
2023-06-04 Dmitry Selyutininsndb/db: support extras command
2023-06-04 Dmitry Selyutininsndb/db: change naming a bit
2023-06-04 Dmitry Selyutininsndb/db: introduce instruction argument type
2023-06-03 Luke Kenneth... fix (most) unit tests in test_pysvp64dis.py
2023-06-03 Luke Kenneth... must check *implicit* SelType which comes from the...
2023-06-03 Luke Kenneth... rename "none" __repr__ to "NONE" in SVExtra and SelType
2023-06-03 Dmitry Selyutininsndb/db: simplify commands structure
2023-06-03 Dmitry Selyutininsndb/db: support pcode command
2023-06-03 Dmitry Selyutininsndb/dis: rename into disasm for no good reason
2023-06-03 Dmitry Selyutininsndb/db: support log option
2023-06-03 Luke Kenneth... correct RS/RA/CR0 for rlwinm which is 2P-1S1D
2023-06-03 Dmitry Selyutininsndb/db: support operands command
2023-06-03 Dmitry Selyutininsndb/db: refactor classes hierarchy
2023-06-03 Dmitry Selyutininsndb/db: deindent classes
2023-06-03 Dmitry Selyutininsndb: rename types into core
2023-06-03 Dmitry Selyutininsndb: revert recent renaming
2023-06-03 Luke Kenneth... openpower.insndb.dis renamed to disasm in setup.py
2023-06-03 Luke Kenneth... using names of modules that are identical to commonly...
2023-06-03 Luke Kenneth... import dis overloads naming of modules already in python3,
2023-06-03 Luke Kenneth... continuing the conversion of LDST_IDX to EXTRA332 type
2023-06-03 Dmitry Selyutininsndb/db: support opcodes command
2023-06-03 Dmitry Selyutininsndb/db: drop redundant method
2023-06-03 Dmitry Selyutininsndb: provide pysvp64db script
2023-06-02 Dmitry Selyutinpysvp64dis: integrate into insndb insndb
2023-06-02 Dmitry Selyutinpysvp64asm: integrate into insndb
2023-06-02 Dmitry Selyutinpower_insn: decouple into separate module
2023-06-01 Dmitry Selyutinpower_insn: disassemble RA0 and RT0 correctly
2023-06-01 Dmitry Selyutinpower_insn: forbid r0 for RA0 and RT0
2023-06-01 Dmitry Selyutinpower_enums: introduce Reg pair property
2023-06-01 Dmitry Selyutinpower_enums: introduce Reg or_zero property
2023-06-01 Dmitry Selyutinpower_insn: drop unused import
2023-06-01 Dmitry Selyutinpower_enums: deprecate SVExtraReg
2023-06-01 Dmitry Selyutinpower_insn: switch to Reg
2023-06-01 Dmitry Selyutinpower_enums: introduce Reg as alias of SVExtraReg
2023-06-01 Dmitry Selyutinpower_insn: guess extra from reg instead of sel
2023-06-01 Dmitry Selyutinpower_enums: provide selector type property
2023-06-01 Dmitry Selyutinpower_enums: deprecate SVExtraRegType
2023-06-01 Dmitry Selyutinpower_insn: switch to SelType
2023-06-01 Dmitry Selyutinpower_enums: introduce SelType as alias of SVExtraRegType
2023-06-01 Dmitry Selyutinpower_insn: completely refactor extras
2023-06-01 Dmitry Selyutinpower_enums: introduce register aliases
2023-06-01 Dmitry Selyutinpower_insn: introduce extras property
2023-06-01 Dmitry Selyutinpower_enums: change SVExtra representation
2023-06-01 Luke Kenneth... far too much memory (58 GB) being used by these unit...
2023-06-01 Luke Kenneth... disable fmv-fcvt tests entirely
2023-06-01 Luke Kenneth... disable fmv / fcvt unit tests as there are such a vast...
2023-06-01 Jacob Lifshayadd expected values to source
2023-06-01 Jacob Lifshayadd worked-out svp64 16-bit maddsubrs test case
2023-06-01 Jacob Lifshaymake maddsubrs show up in SVP64 generated CSVs
2023-06-01 Jacob Lifshayraise error on unhandled instruction kind
2023-06-01 Jacob Lifshaylog no longer raises internal exceptions and has more...
2023-06-01 Jacob Lifshayformat code
2023-06-01 Jacob Lifshayincrease ci maxfail to 10
2023-05-31 Dmitry Selyutintest_pysvp64dis.py: add tests for broken extras
2023-05-31 Jacob Lifshayfcvtfg works!
2023-05-31 Jacob Lifshayadd rest of bfp* functions needed for fcvtfg
2023-05-31 Jacob Lifshayuse raise_syntax_error for `IndentationError`s as well
2023-05-30 Jacob Lifshayadd support for checking sprs and msr in unit tests
2023-05-30 Jacob Lifshayuse a different default MSR value for unit tests since...
2023-05-29 Andrey Miroshnikovinorder.py: Typo fixes.
2023-05-28 Andrey Miroshnikovinorder.py: Added draft get_input/output_regs functions.
2023-05-14 Dmitry Selyutinpower_insn: fix broken extra_idx
2023-05-14 Dmitry Selyutinpower_enums: fix incorrect naming
2023-05-27 Luke Kenneth... add P2M type - 1P 2P 2PM needed for new LD/ST-Indexed...
2023-05-27 Luke Kenneth... https://bugs.libre-soc.org/show_bug.cgi?id=1091
2023-05-27 Luke Kenneth... add .py? gitignore
2023-05-27 Luke Kenneth... rename sm to SH for shift-and-add instructions
2023-05-24 Luke Kenneth... note on FP Exception about DDFF VLi=0/1
2023-05-24 Jacob Lifshaytest fcvttgo. with traps enabled
2023-05-24 Jacob LifshayISACaller: generate FP trap
2023-05-24 Jacob Lifshaytest fcvttgo. with VE=1 too
2023-05-24 Jacob Lifshayfcvttg[s][o][.] needs EXTRA_UNINIT_REGS: RT
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