Implement RVC draft

[riscv-isa-sim.git] / configure

diff --git a/configure b/configure
index 0152a3389562c7f4a43432be5d9db2f010983d28..bed5307c44d54087f1411f7b8a559ccbe0229b3b 100755 (executable)
--- a/configure
+++ b/configure
@@ -665,6 +665,7 @@ enable_stow
 enable_optional_subprojects
 with_fesvr
 enable_fpu
+enable_rvc
 enable_64bit
 enable_commitlog
 enable_histogram
@@ -1300,6 +1301,7 @@ Optional Features:
   --enable-optional-subprojects
                           Enable all optional subprojects
   --disable-fpu           Disable floating-point
+  --disable-rvc           Disable RISC-V Compressed
   --disable-64bit         Disable 64-bit mode
   --enable-commitlog      Enable commit log generation
   --enable-histogram      Enable PC histogram generation
@@ -4095,6 +4097,19 @@ if test "x$enable_fpu" != "xno"; then :
 $as_echo "#define RISCV_ENABLE_FPU /**/" >>confdefs.h
 
 
+fi
+
+# Check whether --enable-rvc was given.
+if test "${enable_rvc+set}" = set; then :
+  enableval=$enable_rvc;
+fi
+
+if test "x$enable_rvc" != "xno"; then :
+
+
+$as_echo "#define RISCV_ENABLE_RVC /**/" >>confdefs.h
+
+
 fi
 
 # Check whether --enable-64bit was given.