Fix 2 trigger corner cases. (#229)

[riscv-isa-sim.git] / riscv / execute.cc

diff --git a/riscv/execute.cc b/riscv/execute.cc
index b110d093d51a8950b376d37e137b3e9c4c48dfff..e639e90462cf9063404f5cfde99b712ad201b94f 100644 (file)
--- a/riscv/execute.cc
+++ b/riscv/execute.cc
@@ -130,9 +130,11 @@ void processor_t::step(size_t n)
         {
           if (unlikely(!state.serialized && state.single_step == state.STEP_STEPPED)) {
             state.single_step = state.STEP_NONE;
-            enter_debug_mode(DCSR_CAUSE_STEP);
-            // enter_debug_mode changed state.pc, so we can't just continue.
-            break;
+            if (state.dcsr.cause == DCSR_CAUSE_NONE) {
+              enter_debug_mode(DCSR_CAUSE_STEP);
+              // enter_debug_mode changed state.pc, so we can't just continue.
+              break;
+            }
           }
 
           if (unlikely(state.single_step == state.STEP_STEPPING)) {