C.LWSP and C.LDSP with rd=0 are legal instructions

[riscv-isa-sim.git] / riscv / insns / c_flwsp.h

diff --git a/riscv/insns/c_flwsp.h b/riscv/insns/c_flwsp.h
index 79058c40a37d7b971640fc9877dc4be9ee91303b..d1e14fe8631ae68f9f2d4abb87b65b221a8a32b8 100644 (file)
--- a/riscv/insns/c_flwsp.h
+++ b/riscv/insns/c_flwsp.h
@@ -4,6 +4,5 @@ if (xlen == 32) {
   require_fp;
   WRITE_FRD(f32(MMU.load_uint32(RVC_SP + insn.rvc_lwsp_imm())));
 } else { // c.ldsp
-  require(insn.rvc_rd() != 0);
   WRITE_RD(MMU.load_int64(RVC_SP + insn.rvc_ldsp_imm()));
 }