C.LWSP and C.LDSP with rd=0 are legal instructions

[riscv-isa-sim.git] / riscv / insns / c_lwsp.h

diff --git a/riscv/insns/c_lwsp.h b/riscv/insns/c_lwsp.h
index b3d74dbf087fb09553ca438bf4c44629ecfdc032..ed4dcf30887e4e299fd2cff5835a4faf521dc3e5 100644 (file)
--- a/riscv/insns/c_lwsp.h
+++ b/riscv/insns/c_lwsp.h
@@ -1,3 +1,2 @@
 require_extension('C');
-require(insn.rvc_rd() != 0);
 WRITE_RD(MMU.load_int32(RVC_SP + insn.rvc_lwsp_imm()));