Fix implementation of FMIN/FMAX NaN case

[riscv-isa-sim.git] / riscv / insns / fmin_d.h

diff --git a/riscv/insns/fmin_d.h b/riscv/insns/fmin_d.h
index 486faa5622f952d81618495f48ae42245eeff39f..5cf349d47ee4dda3e850942059b302d108071099 100644 (file)
--- a/riscv/insns/fmin_d.h
+++ b/riscv/insns/fmin_d.h
@@ -2,7 +2,8 @@ require_extension('D');
 require_fp;
 bool less = f64_lt_quiet(f64(FRS1), f64(FRS2)) ||
             (f64_eq(f64(FRS1), f64(FRS2)) && (f64(FRS1).v & F64_SIGN));
-WRITE_FRD(less || isNaNF64UI(f64(FRS2).v) ? FRS1 : FRS2);
 if (isNaNF64UI(f64(FRS1).v) && isNaNF64UI(f64(FRS2).v))
   WRITE_FRD(f64(defaultNaNF64UI));
+else
+  WRITE_FRD(less || isNaNF64UI(f64(FRS2).v) ? FRS1 : FRS2);
 set_fp_exceptions;