Fix implementation of FMIN/FMAX NaN case

[riscv-isa-sim.git] / riscv / insns / fmin_q.h

diff --git a/riscv/insns/fmin_q.h b/riscv/insns/fmin_q.h
index 675c7fd70ca177ba005d18628090962836978e3e..fcb9526efd6e5d3d8f536716e4478812776ad03c 100644 (file)
--- a/riscv/insns/fmin_q.h
+++ b/riscv/insns/fmin_q.h
@@ -2,7 +2,8 @@ require_extension('Q');
 require_fp;
 bool less = f128_lt_quiet(f128(FRS1), f128(FRS2)) ||
             (f128_eq(f128(FRS1), f128(FRS2)) && (f128(FRS1).v[1] & F64_SIGN));
-WRITE_FRD(less || isNaNF128(f128(FRS2)) ? FRS1 : FRS2);
 if (isNaNF128(f128(FRS1)) && isNaNF128(f128(FRS2)))
   WRITE_FRD(f128(defaultNaNF128()));
+else
+  WRITE_FRD(less || isNaNF128(f128(FRS2)) ? FRS1 : FRS2);
 set_fp_exceptions;