benchmarks/common/crt.S

   1 # See LICENSE for license details.
   2
   3 #include "encoding.h"
   4
   5 #if __riscv_xlen == 64
   6 # define LREG ld
   7 # define SREG sd
   8 # define REGBYTES 8
   9 #else
  10 # define LREG lw
  11 # define SREG sw
  12 # define REGBYTES 4
  13 #endif
  14
  15   .section ".text.init"
  16   .globl _start
  17 _start:
  18   li  x1, 0
  19   li  x2, 0
  20   li  x3, 0
  21   li  x4, 0
  22   li  x5, 0
  23   li  x6, 0
  24   li  x7, 0
  25   li  x8, 0
  26   li  x9, 0
  27   li  x10,0
  28   li  x11,0
  29   li  x12,0
  30   li  x13,0
  31   li  x14,0
  32   li  x15,0
  33   li  x16,0
  34   li  x17,0
  35   li  x18,0
  36   li  x19,0
  37   li  x20,0
  38   li  x21,0
  39   li  x22,0
  40   li  x23,0
  41   li  x24,0
  42   li  x25,0
  43   li  x26,0
  44   li  x27,0
  45   li  x28,0
  46   li  x29,0
  47   li  x30,0
  48   li  x31,0
  49
  50   # enable FPU and accelerator if present
  51   li t0, MSTATUS_FS | MSTATUS_XS
  52   csrs mstatus, t0
  53
  54   # make sure XLEN agrees with compilation choice
  55   li t0, 1
  56   slli t0, t0, 31
  57 #if __riscv_xlen == 64
  58   bgez t0, 1f
  59 #else
  60   bltz t0, 1f
  61 #endif
  62 2:
  63   li a0, 1
  64   sw a0, tohost, t0
  65   j 2b
  66 1:
  67
  68 #ifdef __riscv_flen
  69   # initialize FPU if we have one
  70   la t0, 1f
  71   csrw mtvec, t0
  72
  73   fssr    x0
  74   fmv.s.x f0, x0
  75   fmv.s.x f1, x0
  76   fmv.s.x f2, x0
  77   fmv.s.x f3, x0
  78   fmv.s.x f4, x0
  79   fmv.s.x f5, x0
  80   fmv.s.x f6, x0
  81   fmv.s.x f7, x0
  82   fmv.s.x f8, x0
  83   fmv.s.x f9, x0
  84   fmv.s.x f10,x0
  85   fmv.s.x f11,x0
  86   fmv.s.x f12,x0
  87   fmv.s.x f13,x0
  88   fmv.s.x f14,x0
  89   fmv.s.x f15,x0
  90   fmv.s.x f16,x0
  91   fmv.s.x f17,x0
  92   fmv.s.x f18,x0
  93   fmv.s.x f19,x0
  94   fmv.s.x f20,x0
  95   fmv.s.x f21,x0
  96   fmv.s.x f22,x0
  97   fmv.s.x f23,x0
  98   fmv.s.x f24,x0
  99   fmv.s.x f25,x0
 100   fmv.s.x f26,x0
 101   fmv.s.x f27,x0
 102   fmv.s.x f28,x0
 103   fmv.s.x f29,x0
 104   fmv.s.x f30,x0
 105   fmv.s.x f31,x0
 106 1:
 107 #endif
 108
 109   # initialize trap vector
 110   la t0, trap_entry
 111   csrw mtvec, t0
 112
 113   # initialize global pointer
 114 .option push
 115 .option norelax
 116   la gp, __global_pointer$
 117 .option pop
 118
 119   la  tp, _end + 63
 120   and tp, tp, -64
 121
 122   # get core id
 123   csrr a0, mhartid
 124   # for now, assume only 1 core
 125   li a1, 1
 126 1:bgeu a0, a1, 1b
 127
 128   # give each core 128KB of stack + TLS
 129 #define STKSHIFT 17
 130   sll a2, a0, STKSHIFT
 131   add tp, tp, a2
 132   add sp, a0, 1
 133   sll sp, sp, STKSHIFT
 134   add sp, sp, tp
 135
 136   j _init
 137
 138   .align 2
 139 trap_entry:
 140   addi sp, sp, -272
 141
 142   SREG x1, 1*REGBYTES(sp)
 143   SREG x2, 2*REGBYTES(sp)
 144   SREG x3, 3*REGBYTES(sp)
 145   SREG x4, 4*REGBYTES(sp)
 146   SREG x5, 5*REGBYTES(sp)
 147   SREG x6, 6*REGBYTES(sp)
 148   SREG x7, 7*REGBYTES(sp)
 149   SREG x8, 8*REGBYTES(sp)
 150   SREG x9, 9*REGBYTES(sp)
 151   SREG x10, 10*REGBYTES(sp)
 152   SREG x11, 11*REGBYTES(sp)
 153   SREG x12, 12*REGBYTES(sp)
 154   SREG x13, 13*REGBYTES(sp)
 155   SREG x14, 14*REGBYTES(sp)
 156   SREG x15, 15*REGBYTES(sp)
 157   SREG x16, 16*REGBYTES(sp)
 158   SREG x17, 17*REGBYTES(sp)
 159   SREG x18, 18*REGBYTES(sp)
 160   SREG x19, 19*REGBYTES(sp)
 161   SREG x20, 20*REGBYTES(sp)
 162   SREG x21, 21*REGBYTES(sp)
 163   SREG x22, 22*REGBYTES(sp)
 164   SREG x23, 23*REGBYTES(sp)
 165   SREG x24, 24*REGBYTES(sp)
 166   SREG x25, 25*REGBYTES(sp)
 167   SREG x26, 26*REGBYTES(sp)
 168   SREG x27, 27*REGBYTES(sp)
 169   SREG x28, 28*REGBYTES(sp)
 170   SREG x29, 29*REGBYTES(sp)
 171   SREG x30, 30*REGBYTES(sp)
 172   SREG x31, 31*REGBYTES(sp)
 173
 174   csrr a0, mcause
 175   csrr a1, mepc
 176   mv a2, sp
 177   jal handle_trap
 178   csrw mepc, a0
 179
 180   # Remain in M-mode after eret
 181   li t0, MSTATUS_MPP
 182   csrs mstatus, t0
 183
 184   LREG x1, 1*REGBYTES(sp)
 185   LREG x2, 2*REGBYTES(sp)
 186   LREG x3, 3*REGBYTES(sp)
 187   LREG x4, 4*REGBYTES(sp)
 188   LREG x5, 5*REGBYTES(sp)
 189   LREG x6, 6*REGBYTES(sp)
 190   LREG x7, 7*REGBYTES(sp)
 191   LREG x8, 8*REGBYTES(sp)
 192   LREG x9, 9*REGBYTES(sp)
 193   LREG x10, 10*REGBYTES(sp)
 194   LREG x11, 11*REGBYTES(sp)
 195   LREG x12, 12*REGBYTES(sp)
 196   LREG x13, 13*REGBYTES(sp)
 197   LREG x14, 14*REGBYTES(sp)
 198   LREG x15, 15*REGBYTES(sp)
 199   LREG x16, 16*REGBYTES(sp)
 200   LREG x17, 17*REGBYTES(sp)
 201   LREG x18, 18*REGBYTES(sp)
 202   LREG x19, 19*REGBYTES(sp)
 203   LREG x20, 20*REGBYTES(sp)
 204   LREG x21, 21*REGBYTES(sp)
 205   LREG x22, 22*REGBYTES(sp)
 206   LREG x23, 23*REGBYTES(sp)
 207   LREG x24, 24*REGBYTES(sp)
 208   LREG x25, 25*REGBYTES(sp)
 209   LREG x26, 26*REGBYTES(sp)
 210   LREG x27, 27*REGBYTES(sp)
 211   LREG x28, 28*REGBYTES(sp)
 212   LREG x29, 29*REGBYTES(sp)
 213   LREG x30, 30*REGBYTES(sp)
 214   LREG x31, 31*REGBYTES(sp)
 215
 216   addi sp, sp, 272
 217   mret
 218
 219 .section ".tdata.begin"
 220 .globl _tdata_begin
 221 _tdata_begin:
 222
 223 .section ".tdata.end"
 224 .globl _tdata_end
 225 _tdata_end:
 226
 227 .section ".tbss.end"
 228 .globl _tbss_end
 229 _tbss_end:
 230
 231 .section ".tohost","aw",@progbits
 232 .align 6
 233 .globl tohost
 234 tohost: .dword 0
 235 .align 6
 236 .globl fromhost
 237 fromhost: .dword 0