isa/macros/simplev/sv_test_macros.h

   1 #define SV_REG_CSR( type, regkey, elwidth, regidx, isvec, packed ) \
   2   (regkey | (elwidth<<5) | (type<<7) | (regidx<<8) | (isvec<<14) | (packed<<15))
   3
   4 #define SV_PRED_CSR( type, regkey, zero, inv, regidx, active ) \
   5   (regkey | (zero<<5) | (inv<<6) | (type<<7) | (regidx<<8) | (active<<14))
   6
   7 #define SET_SV_CSR( type, regkey, elwidth, regidx, isvec, packed ) \
   8         li     x1, SV_REG_CSR( type, regkey, elwidth, regidx, isvec, packed ); \
   9         csrrw  x0, 0x4c0, x1
  10
  11 #define SET_SV_PRED_CSR( type, regkey, zero, inv, regidx, active ) \
  12         li     x1, SV_PRED_CSR( type, regkey, zero, inv, regidx, active ); \
  13         csrrw  x0, 0x4c8, x1
  14
  15 #define SET_SV_2CSRS( c1, c2 ) \
  16         li     x1, c1 | ((c2)<<16); \
  17         csrrw  x0, 0x4c0, x1
  18
  19 #define SET_SV_2PREDCSRS( c1, c2 ) \
  20         li     x1, c1 | ((c2)<<16); \
  21         csrrw  x0, 0x4c8, x1
  22
  23 #define CLR_SV_CSRS( ) csrrw   x0, 0x4c0, 0
  24 #define CLR_SV_PRED_CSRS( ) csrrw   x0, 0x4c8, 0
  25
  26 #define SET_SV_MVL( val ) csrrwi   x0, 0x4f2, val
  27 #define SET_SV_VL( val )  csrrwi   x0, 0x4f0, val
  28
  29 #define SV_LD_DATA( reg, from, offs ) \
  30         la      x1, from; \
  31         lw      reg, offs(x1)
  32
  33 #define SV_FLD_DATA( reg, from, offs ) \
  34         la      x1, from; \
  35         fld     reg, offs(x1)
  36
  37 #define TEST_SV_IMM( reg, imm ) \
  38         li      t6, imm; \
  39         bne     reg, t6, fail
  40
  41 #define TEST_SV_FD( flags, freg, from, offs ) \
  42         fsflags x2, x0; \
  43         li      x1, flags; \
  44         bne     x2, x1, fail; \
  45         la      x1, from; \
  46         ld      x1, offs(x1); \
  47         fmv.x.d x2, freg; \
  48         bne     x2, x1, fail