3b0334879b3debdd8879881b13cb98666c084065
[riscv-tests.git] / isa / rv64si / ipi.S
1 #*****************************************************************************
2 # ipi.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test interprocessor interrupts.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV64S
12 RVTEST_CODE_BEGIN
13
14 # clear pending IPIs then enable interrupts
15 la a0, handler
16 csrw evec, a0
17 csrw clear_ipi, x0
18 li a0, SR_EI | (1 << (IRQ_IPI + SR_IM_SHIFT))
19 csrs status, a0
20
21 # wait for all cores to boot
22 la a0, coreid
23 li a1, 1
24 amoadd.w x0, a1, 0(a0)
25 lw a3, 4(x0)
26 1: lw a1, 0(a0)
27 blt a1, a3, 1b
28
29 # IPI dominoes
30 csrr a0, hartid
31 1: bnez a0, 1b
32 add a0, a0, 1
33 rem a0, a0, a3
34 csrw send_ipi, a0
35 1: b 1b
36
37 handler:
38 csrr a0, hartid
39 bnez a0, 2f
40 RVTEST_PASS
41
42 TEST_PASSFAIL
43
44 2: add a0, a0, 1
45 rem a0, a0, a3
46 csrw send_ipi, a0
47 1: b 1b
48
49 RVTEST_CODE_END
50
51 .data
52 RVTEST_DATA_BEGIN
53
54 TEST_DATA
55
56 coreid: .word 0
57 foo: .word 0
58
59 RVTEST_DATA_END