de026f4c10d6ea02ac6faa2395e4eeff984fa714
[riscv-tests.git] / isa / rv64sv / illegal_vt_inst.S
1 #*****************************************************************************
2 # illegal_vt_inst.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test illegal vt instruction trap.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV64S
12 RVTEST_CODE_BEGIN
13
14 setpcr status, SR_EI # enable interrupt
15
16 la a3,handler
17 mtpcr a3,evec # set exception handler
18
19 mfpcr a3,status
20 li a4,(1 << IRQ_COP)
21 slli a4,a4,SR_IM_SHIFT
22 or a3,a3,a4 # enable IM[COP]
23 mtpcr a3,status
24
25 vsetcfg 32,0
26 li a3,4
27 vsetvl a3,a3
28
29 la a3,src1
30 la a4,src2
31 vld vx2,a3
32 vld vx3,a4
33 lui a0,%hi(vtcode1)
34 vf %lo(vtcode1)(a0)
35 fence
36
37 vtcode1:
38 add x2,x2,x3
39 illegal:
40 .word 0x0
41 stop
42
43 vtcode2:
44 add x2,x2,x3
45 stop
46
47 handler:
48 vxcptkill
49
50 li x28,2
51
52 # check cause
53 vxcptcause a3
54 li a4,HWACHA_CAUSE_VF_ILLEGAL_INSTRUCTION
55 bne a3,a4,fail
56
57 # check badvaddr
58 vxcptaux a3
59 la a4,illegal
60 bne a3,a4,fail
61
62 # make sure vector unit has cleared out
63 vsetcfg 32,0
64 li a3,4
65 vsetvl a3,a3
66
67 la a3,src1
68 la a4,src2
69 vld vx2,a3
70 vld vx3,a4
71 lui a0,%hi(vtcode2)
72 vf %lo(vtcode2)(a0)
73 la a5,dest
74 vsd vx2,a5
75 fence
76
77 ld a1,0(a5)
78 li a2,5
79 li x28,2
80 bne a1,a2,fail
81 ld a1,8(a5)
82 li x28,3
83 bne a1,a2,fail
84 ld a1,16(a5)
85 li x28,4
86 bne a1,a2,fail
87 ld a1,24(a5)
88 li x28,5
89 bne a1,a2,fail
90
91 TEST_PASSFAIL
92
93 RVTEST_CODE_END
94
95 .data
96 RVTEST_DATA_BEGIN
97
98 TEST_DATA
99
100 src1:
101 .dword 1
102 .dword 2
103 .dword 3
104 .dword 4
105 src2:
106 .dword 4
107 .dword 3
108 .dword 2
109 .dword 1
110 dest:
111 .dword 0xdeadbeefcafebabe
112 .dword 0xdeadbeefcafebabe
113 .dword 0xdeadbeefcafebabe
114 .dword 0xdeadbeefcafebabe
115
116 RVTEST_DATA_END