d7c96b3f0c8dc0ffeb248db849a375067eeff35d
[riscv-tests.git] / isa / rv64sv / ma_vt_inst.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # ma_vt_inst.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test misaligned vt instruction trap.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV64SV
14 RVTEST_CODE_BEGIN
15
16 la a3,handler
17 csrw stvec,a3 # set exception handler
18
19 vsetcfg 32,0
20 li a3,4
21 vsetvl a3,a3
22
23 lui a0,%hi(vtcode1+2)
24 vf %lo(vtcode1+2)(a0)
25 1: j 1b
26
27 vtcode1:
28 add x2,x2,x3
29 stop
30
31 handler:
32 vxcptkill
33
34 li TESTNUM,2
35
36 # check cause
37 csrr a3, scause
38 li a4,HWACHA_CAUSE_VF_MISALIGNED_FETCH
39 bne a3,a4,fail
40
41 # check badvaddr
42 csrr a3, sbadaddr
43 la a4,vtcode1+2
44 andi a3, a3, -4 # mask off lower bits so that may
45 andi a4, a4, -4 # ignore impl. specific behavior
46 bne a3,a4,fail
47
48 # make sure vector unit has cleared out
49 vsetcfg 32,0
50 li a3,4
51 vsetvl a3,a3
52
53 la a3,src1
54 la a4,src2
55 vld vx2,a3
56 vld vx3,a4
57 lui a0,%hi(vtcode1)
58 vf %lo(vtcode1)(a0)
59 la a5,dest
60 vsd vx2,a5
61 fence
62
63 ld a1,0(a5)
64 li a2,5
65 li TESTNUM,2
66 bne a1,a2,fail
67 ld a1,8(a5)
68 li TESTNUM,3
69 bne a1,a2,fail
70 ld a1,16(a5)
71 li TESTNUM,4
72 bne a1,a2,fail
73 ld a1,24(a5)
74 li TESTNUM,5
75 bne a1,a2,fail
76
77 TEST_PASSFAIL
78
79 RVTEST_CODE_END
80
81 .data
82 RVTEST_DATA_BEGIN
83
84 TEST_DATA
85
86 src1:
87 .dword 1
88 .dword 2
89 .dword 3
90 .dword 4
91 src2:
92 .dword 4
93 .dword 3
94 .dword 2
95 .dword 1
96 dest:
97 .dword 0xdeadbeefcafebabe
98 .dword 0xdeadbeefcafebabe
99 .dword 0xdeadbeefcafebabe
100 .dword 0xdeadbeefcafebabe
101
102 RVTEST_DATA_END