1 # See LICENSE for license details.
3 #*****************************************************************************
5 #-----------------------------------------------------------------------------
7 # Test misaligned vt instruction trap.
10 #include "riscv_test.h"
11 #include "test_macros.h"
17 csrw stvec,a3 # set exception handler
38 li a4,HWACHA_CAUSE_VF_MISALIGNED_FETCH
44 andi a3, a3, -4 # mask off lower bits so that may
45 andi a4, a4, -4 # ignore impl. specific behavior
48 # make sure vector unit has cleared out
97 .dword 0xdeadbeefcafebabe
98 .dword 0xdeadbeefcafebabe
99 .dword 0xdeadbeefcafebabe
100 .dword 0xdeadbeefcafebabe