5a5760d1eea9c9523e372c0642e1128b061a2f61
[riscv-tests.git] / isa / rv64uv / vvadd_packed.S
1 #*****************************************************************************
2 # vvadd_packed.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test packed half-precision vvadd
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV64UV
12 RVTEST_CODE_BEGIN
13
14 li x1, 12 # number of test elements
15 move x10, x1
16 vsetucfg x2, 0x2
17 vsetcfg x2, 3, 1
18 loop:
19 vsetvl x4, x1
20 la x2, addr
21 vmsv vx1, x2
22 la x3, test
23 vf 0(x3)
24 sub x1, x1, x4
25 bnez x1, loop
26 fence
27 j check
28
29 enable_accel:
30 csrr x2, status
31 ori x2, x2, 0x100
32 csrw status, x2
33 # test if set
34 csrr x2, status
35 andi x2, x2, 0x100
36 beqz x2, fail
37 ret
38
39 enable_fp:
40 csrr x2, status
41 ori x2, x2, 0x10
42 csrw status, x2
43 # test if set
44 csrr x2, status
45 andi x2, x2, 0x10
46 beqz x2, fail
47 ret
48
49 test:
50 utidx x2
51 slli x2, x2, 2
52 add x1, x1, x2
53 flh f0, 0(x1)
54 fmul.h f0, f0, f0
55 fsh f0, 0(x1)
56 stop
57
58 check:
59 la x2, addr
60 la x4, expc
61
62 check_loop:
63 lw x3, 0(x4)
64 lw x1, 0(x2)
65 bne x1, x3, fail
66 addi x10, x10, -1
67 addi x4, x4, 0x4
68 addi x2, x2, 0x4
69 bnez x10, check_loop
70 j pass
71
72 TEST_PASSFAIL
73
74 .data
75 RVTEST_DATA_BEGIN
76
77 TEST_DATA
78
79 addr: .word 0x4000
80 .word 0x4400
81 .word 0x4800
82 .word 0x5000
83 .word 0x4001
84 .word 0x4401
85 .word 0x4801
86 .word 0x5001
87 .word 0x4002
88 .word 0x4402
89 .word 0x4802
90 .word 0x5002
91
92 expc: .word 0x4400
93 .word 0x4c00
94 .word 0x5400
95 .word 0x6400
96 .word 0x4402
97 .word 0x4c02
98 .word 0x5402
99 .word 0x6402
100 .word 0x4404
101 .word 0x4c04
102 .word 0x5404
103 .word 0x6404
104
105 RVTEST_DATA_END