Verify that F18 does not exist on FPU-less targets

[riscv-tests.git] / debug / gdbserver.py

diff --git a/debug/gdbserver.py b/debug/gdbserver.py
index eabf445065c13bcccb714cfe3eec64d70cee0e06..d7092a8aaf62e28ac9b18e5ba909128634fcc20f 100755 (executable)
--- a/debug/gdbserver.py
+++ b/debug/gdbserver.py
@@ -106,23 +106,26 @@ class SimpleT1Test(SimpleRegisterTest):
 
 class SimpleF18Test(SimpleRegisterTest):
     def check_reg(self, name, alias):
-        self.gdb.p_raw("$mstatus=$mstatus | 0x00006000")
-        self.gdb.stepi()
-        a = random.random()
-        b = random.random()
-        self.gdb.p_raw("$%s=%f" % (name, a))
-        assertLess(abs(float(self.gdb.p_raw("$%s" % alias)) - a), .001)
-        self.gdb.stepi()
-        assertLess(abs(float(self.gdb.p_raw("$%s" % name)) - a), .001)
-        assertLess(abs(float(self.gdb.p_raw("$%s" % alias)) - a), .001)
-        self.gdb.p_raw("$%s=%f" % (alias, b))
-        assertLess(abs(float(self.gdb.p_raw("$%s" % name)) - b), .001)
-        self.gdb.stepi()
-        assertLess(abs(float(self.gdb.p_raw("$%s" % name)) - b), .001)
-        assertLess(abs(float(self.gdb.p_raw("$%s" % alias)) - b), .001)
-
-    def early_applicable(self):
-        return self.hart.extensionSupported('F')
+        if self.hart.extensionSupported('F'):
+            self.gdb.p_raw("$mstatus=$mstatus | 0x00006000")
+            self.gdb.stepi()
+            a = random.random()
+            b = random.random()
+            self.gdb.p_raw("$%s=%f" % (name, a))
+            assertLess(abs(float(self.gdb.p_raw("$%s" % alias)) - a), .001)
+            self.gdb.stepi()
+            assertLess(abs(float(self.gdb.p_raw("$%s" % name)) - a), .001)
+            assertLess(abs(float(self.gdb.p_raw("$%s" % alias)) - a), .001)
+            self.gdb.p_raw("$%s=%f" % (alias, b))
+            assertLess(abs(float(self.gdb.p_raw("$%s" % name)) - b), .001)
+            self.gdb.stepi()
+            assertLess(abs(float(self.gdb.p_raw("$%s" % name)) - b), .001)
+            assertLess(abs(float(self.gdb.p_raw("$%s" % alias)) - b), .001)
+        else:
+            output = self.gdb.p_raw("$" + name)
+            assertEqual(output, "void")
+            output = self.gdb.p_raw("$" + alias)
+            assertEqual(output, "void")
 
     def test(self):
         self.check_reg("f18", "fs2")
@@ -207,7 +210,7 @@ class MemTestBlock(GdbTest):
         self.gdb.command("dump ihex memory %s 0x%x 0x%x" % (b.name,
             self.hart.ram, self.hart.ram + self.length))
         self.gdb.command("shell cat %s" % b.name)
-        for line in b:
+        for line in b.xreadlines():
             record_type, address, line_data = ihex_parse(line)
             if record_type == 0:
                 written_data = data[address:address+len(line_data)]
@@ -396,6 +399,8 @@ class Registers(DebugTest):
             output = self.gdb.command(cmd)
             for reg in ('zero', 'ra', 'sp', 'gp', 'tp'):
                 assertIn(reg, output)
+            for line in output.splitlines():
+                assertRegexpMatches(line, r"^\S")
 
         #TODO
         # mcpuid is one of the few registers that should have the high bit set
@@ -814,6 +819,14 @@ class PrivTest(GdbTest):
 class PrivRw(PrivTest):
     def test(self):
         """Test reading/writing priv."""
+        # Disable physical memory protection by allowing U mode access to all
+        # memory.
+        self.gdb.p("$pmpcfg0=0xf")  # TOR, R, W, X
+        self.gdb.p("$pmpaddr0=0x%x" %
+                ((self.hart.ram + self.hart.ram_size) >> 2))
+
+        # Leave the PC at _start, where the first 4 instructions should be
+        # legal in any mode.
         for privilege in range(4):
             self.gdb.p("$priv=%d" % privilege)
             self.gdb.stepi()
@@ -862,9 +875,7 @@ def main():
     global parsed   # pylint: disable=global-statement
     parsed = parser.parse_args()
     target = targets.target(parsed)
-
-    if parsed.xlen:
-        target.xlen = parsed.xlen
+    testlib.print_log_names = parsed.print_log_names
 
     module = sys.modules[__name__]