#ifndef __TEST_MACROS_SCALAR_H
#define __TEST_MACROS_SCALAR_H
-#define TEST_DATA
#-----------------------------------------------------------------------
# Helper macros
#define TEST_INSERT_NOPS_9 nop; TEST_INSERT_NOPS_8
#define TEST_INSERT_NOPS_10 nop; TEST_INSERT_NOPS_9
+
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
#-----------------------------------------------------------------------
# Tests for instructions with immediate operand
#-----------------------------------------------------------------------
# Tests for vector config instructions
#-----------------------------------------------------------------------
-#define TEST_VVCFGIVL( testnum, nxpr, nfpr, bank, vl, result ) \
+#define TEST_VSETCFGIVL( testnum, nxpr, nfpr, bank, vl, result ) \
TEST_CASE_JUMP( testnum, x1, result, \
- li x2, bank; \
- mtpcr x2, cr18; \
+ li x1, (bank << 12); \
+ vsetcfg x1,nxpr,nfpr; \
li x1, vl; \
- vvcfgivl x1,x1,nxpr,nfpr; \
+ vsetvl x1,x1; \
)
#define TEST_VVCFG( testnum, nxpr, nfpr, bank, vl, result ) \
TEST_CASE_JUMP( testnum, x1, result, \
- li x2, bank; \
- mtpcr x2, cr18; \
- li x1, nxpr; \
- li x2, nfpr; \
- vvcfg x1,x2; \
+ li x1, (bank << 12) | (nfpr << 6) | nxpr; \
+ vsetcfg x1; \
li x1, vl; \
vsetvl x1,x1; \
)
#define TEST_VSETVL( testnum, nxpr, nfpr, bank, vl, result ) \
TEST_CASE_JUMP( testnum, x1, result, \
- li x2, bank; \
- mtpcr x2, cr18; \
- vvcfgivl x0,x0,nxpr,nfpr; \
+ li x1, (bank << 12); \
+ vsetcfg x1,nxpr,nfpr; \
li x1, vl; \
vsetvl x1, x1; \
)
li x5, 2; \
bne x4, x5, 1b \
+
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
#-----------------------------------------------------------------------
# Tests floating-point instructions
#-----------------------------------------------------------------------
#define TEST_FCVT_S_D( testnum, result, val1 ) \
TEST_FP_OP_D_INTERNAL( testnum, double result, val1, 0.0, 0.0, \
- fcvt.s.d f3, f0; fcvt.d.s f3, f3; mftx.d a0, f3)
+ fcvt.s.d f3, f0; fcvt.d.s f3, f3; fmv.x.d a0, f3)
#define TEST_FCVT_D_S( testnum, result, val1 ) \
TEST_FP_OP_S_INTERNAL( testnum, float result, val1, 0.0, 0.0, \
- fcvt.d.s f3, f0; fcvt.s.d f3, f3; mftx.s a0, f3)
+ fcvt.d.s f3, f0; fcvt.s.d f3, f3; fmv.x.s a0, f3)
#define TEST_FP_OP1_S( testnum, inst, result, val1 ) \
TEST_FP_OP_S_INTERNAL( testnum, float result, val1, 0.0, 0.0, \
- inst f3, f0; mftx.s a0, f3)
+ inst f3, f0; fmv.x.s a0, f3)
#define TEST_FP_OP1_D( testnum, inst, result, val1 ) \
TEST_FP_OP_D_INTERNAL( testnum, double result, val1, 0.0, 0.0, \
- inst f3, f0; mftx.d a0, f3)
+ inst f3, f0; fmv.x.d a0, f3)
#define TEST_FP_OP2_S( testnum, inst, result, val1, val2 ) \
TEST_FP_OP_S_INTERNAL( testnum, float result, val1, val2, 0.0, \
- inst f3, f0, f1; mftx.s a0, f3)
+ inst f3, f0, f1; fmv.x.s a0, f3)
#define TEST_FP_OP2_D( testnum, inst, result, val1, val2 ) \
TEST_FP_OP_D_INTERNAL( testnum, double result, val1, val2, 0.0, \
- inst f3, f0, f1; mftx.d a0, f3)
+ inst f3, f0, f1; fmv.x.d a0, f3)
#define TEST_FP_OP3_S( testnum, inst, result, val1, val2, val3 ) \
TEST_FP_OP_S_INTERNAL( testnum, float result, val1, val2, val3, \
- inst f3, f0, f1, f2; mftx.s a0, f3)
+ inst f3, f0, f1, f2; fmv.x.s a0, f3)
#define TEST_FP_OP3_D( testnum, inst, result, val1, val2, val3 ) \
TEST_FP_OP_D_INTERNAL( testnum, double result, val1, val2, val3, \
- inst f3, f0, f1, f2; mftx.d a0, f3)
+ inst f3, f0, f1, f2; fmv.x.d a0, f3)
#define TEST_FP_INT_OP_S( testnum, inst, result, val1, rm ) \
TEST_FP_OP_S_INTERNAL( testnum, word result, val1, 0.0, 0.0, \
lw a3, 0(a0); \
li a0, val1; \
inst f0, a0; \
- mftx.s a0, f0; \
+ fmv.x.s a0, f0; \
bne a0, a3, fail; \
b 1f; \
.align 2; \
ld a3, 0(a0); \
li a0, val1; \
inst f0, a0; \
- mftx.d a0, f0; \
+ fmv.x.d a0, f0; \
bne a0, a3, fail; \
b 1f; \
.align 3; \
.double result; \
1:
-#define TEST_ILLEGAL_VT_REGID( testnum, nxreg, nfreg, inst, reg1, reg2, reg3) \
- mfpcr a0,cr0; \
- li a1,1; \
- slli a3,a1,8; \
- or a0,a0,a1; \
- mtpcr a0,cr0; \
+
+#-----------------------------------------------------------------------
+# RV64SV MACROS
+#-----------------------------------------------------------------------
+
+#define TEST_ILLEGAL_TVEC_REGID( testnum, nxreg, nfreg, inst, reg1, reg2) \
+ setpcr status, SR_EI; \
la a0, handler ## testnum; \
- mtpcr a0, cr3; \
+ mtpcr a0, evec; \
+ vsetcfg nxreg, nfreg; \
li a0, 4; \
- vvcfgivl a0, a0, nxreg, nfreg; \
+ vsetvl a0, a0; \
la a0, src1; \
la a1, src2; \
vld vx2, a0; \
vld vx3, a1; \
lui a0,%hi(vtcode1 ## testnum); \
vf %lo(vtcode1 ## testnum)(a0); \
+ la reg2, dest; \
+illegal ## testnum: \
+ inst reg1, reg2; \
la a3, dest; \
vsd vx2, a3; \
- fence.v.l; \
+ fence; \
vtcode1 ## testnum: \
add x2, x2, x3; \
-illegal ## testnum: \
- inst reg1, reg2, reg3; \
stop; \
vtcode2 ## testnum: \
add x2, x2, x3; \
handler ## testnum: \
vxcptkill; \
li x28,2; \
- mfpcr a0,cr6; \
- li a1,26; \
- bne a0,a1,fail; \
- mfpcr a0,cr2; \
- la a1,illegal ## testnum; \
+ vxcptcause a0; \
+ li a1,HWACHA_CAUSE_TVEC_ILLEGAL_REGID; \
bne a0,a1,fail; \
+ vxcptaux a0; \
+ la a1, illegal ## testnum; \
+ lw a2, 0(a1); \
+ bne a0, a2, fail; \
+ vsetcfg 32,0; \
li a0,4; \
- vvcfgivl a0,a0,32,0; \
+ vsetvl a0,a0; \
la a0,src1; \
la a1,src2; \
vld vx2,a0; \
vf %lo(vtcode2 ## testnum)(a0); \
la a3,dest; \
vsd vx2,a3; \
- fence.v.l; \
+ fence; \
ld a1,0(a3); \
li a2,5; \
li x28,2; \
li x28,5; \
bne a1,a2,fail; \
-#define TEST_ILLEGAL_TVEC_REGID( testnum, nxreg, nfreg, inst, reg1, reg2, aux) \
- mfpcr a0,cr0; \
- li a1,1; \
- slli a2,a1,8; \
- or a0,a0,a1; \
- mtpcr a0,cr0; \
+#define TEST_ILLEGAL_VT_REGID( testnum, nxreg, nfreg, inst, reg1, reg2, reg3) \
+ setpcr status, SR_EI; \
la a0, handler ## testnum; \
- mtpcr a0, cr3; \
+ mtpcr a0, evec; \
+ vsetcfg nxreg, nfreg; \
li a0, 4; \
- vvcfgivl a0, a0, nxreg, nfreg; \
+ vsetvl a0, a0; \
la a0, src1; \
la a1, src2; \
vld vx2, a0; \
vld vx3, a1; \
lui a0,%hi(vtcode1 ## testnum); \
vf %lo(vtcode1 ## testnum)(a0); \
- la reg2, dest; \
-illegal ## testnum: \
- inst reg1, reg2; \
la a3, dest; \
vsd vx2, a3; \
- fence.v.l; \
+ fence; \
vtcode1 ## testnum: \
add x2, x2, x3; \
+illegal ## testnum: \
+ inst reg1, reg2, reg3; \
stop; \
vtcode2 ## testnum: \
add x2, x2, x3; \
handler ## testnum: \
vxcptkill; \
li x28,2; \
- mfpcr a0,cr6; \
- li a1,27; \
+ vxcptcause a0; \
+ li a1,HWACHA_CAUSE_VF_ILLEGAL_REGID; \
bne a0,a1,fail; \
- mfpcr a0, cr2; \
- li a1, aux; \
- bne a0, a1, fail; \
+ vxcptaux a0; \
+ la a1,illegal ## testnum; \
+ bne a0,a1,fail; \
+ vsetcfg 32,0; \
li a0,4; \
- vvcfgivl a0,a0,32,0; \
+ vsetvl a0,a0; \
la a0,src1; \
la a1,src2; \
vld vx2,a0; \
vf %lo(vtcode2 ## testnum)(a0); \
la a3,dest; \
vsd vx2,a3; \
- fence.v.l; \
+ fence; \
ld a1,0(a3); \
li a2,5; \
li x28,2; \
# Pass and fail code (assumes test num is in x28)
#-----------------------------------------------------------------------
-
#define TEST_PASSFAIL \
bne x0, x28, pass; \
fail: \
pass: \
RVTEST_PASS \
+
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+
+#define TEST_DATA
+
#endif