Merge rv64si and rv32si tests

[riscv-tests.git] / isa / rv32si / timer.S

diff --git a/isa/rv32si/timer.S b/isa/rv32si/timer.S
index 40488753112878913b81f6ff7899d94a9833ebd0..a6847aa12343a9f5ed5024c6014eb769f02cf18e 100644 (file)
--- a/isa/rv32si/timer.S
+++ b/isa/rv32si/timer.S
@@ -1,49 +1,7 @@
-#*****************************************************************************
-# timer.S
-#-----------------------------------------------------------------------------
-#
-# Test timer interrupt.
-#
+# See LICENSE for license details.
 
 #include "riscv_test.h"
-#include "test_macros.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV32S
 
-RVTEST_RV32S
-RVTEST_CODE_BEGIN
-
-  la t0, evec
-  csrw evec, t0
-
-  csrr t0, count
-  add t0, t0, 1000
-  csrw compare, t0
-
-  li t1, 1<<23
-  csrs status, t1 # turn on timer IRQ 7
-  csrsi status, 4 # enable interrupts
-
-  li TESTNUM, 2
-  li a0,10000
-loop:
-  div x0, x0, x0
-  addi a0, a0, -1
-  bne a0, x0, loop
-  j fail # assumption is that you can't divide in one cycle
-
-  TEST_PASSFAIL
-
-evec:
-  li TESTNUM, 3
-  li t1, 0x80000000|IRQ_TIMER
-  csrr t0, cause
-  bne t0, t1, fail
-  j pass
-
-RVTEST_CODE_END
-
-  .data
-RVTEST_DATA_BEGIN
-
-  TEST_DATA
-
-RVTEST_DATA_END
+#include "../rv64si/timer.S"