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Add rv32uf tests
[riscv-tests.git] / isa / rv32uf / fsgnj.S
diff --git a/isa/rv32uf/fsgnj.S b/isa/rv32uf/fsgnj.S
new file mode 100644 (file)
index 0000000..6d05a23
--- /dev/null
+++ b/isa/rv32uf/fsgnj.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uf/fsgnj.S"