Pass newly updated -march, -mabi options to gcc

[riscv-tests.git] / isa / rv64mi / ipi.S

diff --git a/isa/rv64mi/ipi.S b/isa/rv64mi/ipi.S
index 457a9cda5c924e4e00efe2131f9d84f945c3adfd..71783107e250478b817b99b5a815a580f5a108c1 100644 (file)
--- a/isa/rv64mi/ipi.S
+++ b/isa/rv64mi/ipi.S
@@ -14,7 +14,7 @@ RVTEST_RV64M
 RVTEST_CODE_BEGIN
 
   # enable interrupts
-  csrs mstatus, MSTATUS_IE
+  csrs mstatus, MSTATUS_MIE
   csrs mie, MIP_MSIP
 
   # get a unique core id
@@ -26,30 +26,16 @@ RVTEST_CODE_BEGIN
   1:li a3, 1
   bgeu a2, a3, 1b
   
-  # wait for all cores to boot
-  1: lw a1, (a0)
-  bltu a1, a3, 1b
-
-  # IPI dominoes
-  csrr a0, mhartid
-  1: bnez a0, 1b
-  add a0, a0, 1
-  rem a0, a0, a3
-  csrw send_ipi, a0
+  # send a self-IPI
+  csrwi mipi, 1
   1: j 1b
 
 mtvec_handler:
-  csrr a0, mhartid
-  bnez a0, 2f
+  bnez a2, fail
   RVTEST_PASS
 
   TEST_PASSFAIL
 
-  2: add a0, a0, 1
-  rem a0, a0, a3
-  csrw send_ipi, a0
-  1: j 1b
-
 RVTEST_CODE_END
 
   .data