Merge branch 'master' of https://github.com/riscv/riscv-tests

[riscv-tests.git] / isa / rv64si / scall.S

diff --git a/isa/rv64si/scall.S b/isa/rv64si/scall.S
index 0579806e9af0770cf7c04eb689e25ec29d055c9e..82f202a361836866ac69c4ab3e7cb392362c07d2 100644 (file)
--- a/isa/rv64si/scall.S
+++ b/isa/rv64si/scall.S
@@ -34,8 +34,8 @@ RVTEST_CODE_BEGIN
   # Otherwise, if in S mode, then U mode must exist and we don't need to check.
   li t0, MSTATUS_MPP
   csrc mstatus, t0
-  csrr t1, mstatus
-  and t0, t0, t1
+  csrr t2, mstatus
+  and t0, t0, t2
   beqz t0, 1f
 
   # If U mode doesn't exist, mcause should indicate ECALL from M mode.