relay hwacha cause/aux to scause/sbadaddr

[riscv-tests.git] / isa / rv64sv / illegal_cfg_nfpr.S

diff --git a/isa/rv64sv/illegal_cfg_nfpr.S b/isa/rv64sv/illegal_cfg_nfpr.S
index 2440cbbf745e9a8fa85988cc134c55a828829855..03227eb2a166dd9d4b356fb6dbc0db04e25df4c6 100644 (file)
--- a/isa/rv64sv/illegal_cfg_nfpr.S
+++ b/isa/rv64sv/illegal_cfg_nfpr.S
@@ -1,3 +1,5 @@
+# See LICENSE for license details.
+
 #*****************************************************************************
 # illegal_tvec_cmd.S
 #-----------------------------------------------------------------------------
@@ -8,20 +10,11 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64S
+RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  setpcr status, SR_EA # enable accelerator
-  setpcr status, SR_EI # enable interrupt
-
   la a3,handler
-  mtpcr a3,evec # set exception handler
-
-  mfpcr a3,status
-  li a4,(1 << IRQ_COP)
-  slli a4,a4,SR_IM_SHIFT
-  or a3,a3,a4 # enable IM[COP]
-  mtpcr a3,status
+  csrw stvec,a3 # set exception handler
 
   li a0,33
   slli a0,a0,6
@@ -34,15 +27,15 @@ vtcode2:
 handler:
   vxcptkill
 
-  li x28,2
+  li TESTNUM,2
 
   # check cause
-  vxcptcause a3
+  csrr a3, scause
   li a4,HWACHA_CAUSE_ILLEGAL_CFG
   bne a3,a4,fail
 
   # check vec irq aux
-  vxcptaux a3
+  csrr a3, sbadaddr
   li a4, 1
   bne a3,a4,fail
 
@@ -63,16 +56,16 @@ handler:
 
   ld a1,0(a5)
   li a2,5
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   ld a1,8(a5)
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   ld a1,16(a5)
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   ld a1,24(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
 
   TEST_PASSFAIL