correctly set SR_EA bit for all vector physical supervisor tests

[riscv-tests.git] / isa / rv64sv / illegal_vt_inst.S

diff --git a/isa/rv64sv/illegal_vt_inst.S b/isa/rv64sv/illegal_vt_inst.S
index d749104cda88dd5977589bc8b3cedd8d32e57add..9bb586b5190f098e37208ea34f83ba00cb9adbb2 100644 (file)
--- a/isa/rv64sv/illegal_vt_inst.S
+++ b/isa/rv64sv/illegal_vt_inst.S
@@ -11,17 +11,21 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
-  mfpcr a3,cr0
-  li a4,1
-  slli a5,a4,8
-  or a3,a3,a4 # enable traps
-  mtpcr a3,cr0
+  setpcr status, SR_EA # enable accelerator
+  setpcr status, SR_EI # enable interrupt
 
   la a3,handler
-  mtpcr a3,cr3 # set exception handler
+  mtpcr a3,evec # set exception handler
 
+  mfpcr a3,status
+  li a4,(1 << IRQ_COP)
+  slli a4,a4,SR_IM_SHIFT
+  or a3,a3,a4 # enable IM[COP]
+  mtpcr a3,status
+
+  vsetcfg 32,0
   li a3,4
-  vvcfgivl a3,a3,32,0
+  vsetvl a3,a3
 
   la a3,src1
   la a4,src2
@@ -29,7 +33,7 @@ RVTEST_CODE_BEGIN
   vld vx3,a4
   lui a0,%hi(vtcode1)
   vf %lo(vtcode1)(a0)
-  fence.v.l
+  fence
 
 vtcode1:
   add x2,x2,x3
@@ -47,18 +51,19 @@ handler:
   li x28,2
 
   # check cause
-  mfpcr a3,cr6
-  li a4,26
+  vxcptcause a3
+  li a4,HWACHA_CAUSE_VF_ILLEGAL_INSTRUCTION
   bne a3,a4,fail
 
   # check badvaddr
-  mfpcr a3,cr2
+  vxcptaux a3
   la a4,illegal
   bne a3,a4,fail
 
   # make sure vector unit has cleared out
+  vsetcfg 32,0
   li a3,4
-  vvcfgivl a3,a3,32,0
+  vsetvl a3,a3
 
   la a3,src1
   la a4,src2
@@ -68,7 +73,7 @@ handler:
   vf %lo(vtcode2)(a0)
   la a5,dest
   vsd vx2,a5
-  fence.v.l
+  fence
 
   ld a1,0(a5)
   li a2,5