correctly set SR_EA bit for all vector physical supervisor tests

[riscv-tests.git] / isa / rv64sv / illegal_vt_inst.S

diff --git a/isa/rv64sv/illegal_vt_inst.S b/isa/rv64sv/illegal_vt_inst.S
index de026f4c10d6ea02ac6faa2395e4eeff984fa714..9bb586b5190f098e37208ea34f83ba00cb9adbb2 100644 (file)
--- a/isa/rv64sv/illegal_vt_inst.S
+++ b/isa/rv64sv/illegal_vt_inst.S
@@ -11,6 +11,7 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
+  setpcr status, SR_EA # enable accelerator
   setpcr status, SR_EI # enable interrupt
 
   la a3,handler