Merge branch 'master' of github.com:ucb-bar/riscv-tests

[riscv-tests.git] / isa / rv64uv / flw.S

diff --git a/isa/rv64uv/flw.S b/isa/rv64uv/flw.S
index 0a42b7b131270b2ab56763b154d13b811204f54e..02844894ae33698ba7a8582b98b1c512ab5d064a 100644 (file)
--- a/isa/rv64uv/flw.S
+++ b/isa/rv64uv/flw.S
@@ -8,11 +8,12 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
+  vsetcfg 4,1
   li a4,2048
-  vvcfgivl a4,a4,4,1
+  vsetvl a4,a4
 
   la a5,src
   vmsv vx2,a5
@@ -20,12 +21,12 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode)(a0)
   la a6,dest
   vfsw vf0,a6
-  fence.v.l
+  fence
 
   li a2,0
 loop:
   lw a0,0(a6)
-  addi x28,a2,2
+  addi TESTNUM,a2,2
   lw a1,0(a5)
   bne a0,a1,fail
   addi a6,a6,4