Add another FP recoding test case

[riscv-tests.git] / isa / rv64uv / sh.S

diff --git a/isa/rv64uv/sh.S b/isa/rv64uv/sh.S
index e35a77b2ea552bad4164c2ab53a0e0c9ef6a6c43..c87f070875c02192b5bc624f8a7f31e4d4c89e65 100644 (file)
--- a/isa/rv64uv/sh.S
+++ b/isa/rv64uv/sh.S
@@ -1,3 +1,5 @@
+# See LICENSE for license details.
+
 #*****************************************************************************
 # sh.S
 #-----------------------------------------------------------------------------
@@ -8,7 +10,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 16,0
@@ -39,7 +41,7 @@ loop:
   ld a1,0(a5)
   sll a3,a1,48
   srl a3,a3,48
-  addi x28,a2,2
+  addi TESTNUM,a2,2
   bne a0,a3,fail
   addi a6,a6,8
   addi a5,a5,8