cpu.py

   1 """
   2 /*
   3  * Copyright 2018 Jacob Lifshay
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy
   6  * of this software and associated documentation files (the "Software"), to deal
   7  * in the Software without restriction, including without limitation the rights
   8  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9  * copies of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in all
  13  * copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  18  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  */
  24 `timescale 1ns / 1ps
  25 `include "riscv.vh"
  26 `include "cpu.vh"
  27 """
  28
  29 import string
  30 from migen import *
  31 from migen.fhdl import verilog
  32 from migen.fhdl.structure import _Operator
  33
  34 from riscvdefs import *
  35 from cpudefs import *
  36
  37 class MemoryInterface:
  38     fetch_address = Signal(32, name="memory_interface_fetch_address") # XXX [2:]
  39     fetch_data = Signal(32, name="memory_interface_fetch_data")
  40     fetch_valid = Signal(name="memory_interface_fetch_valid")
  41     rw_address= Signal(32, name="memory_interface_rw_address") # XXX [2:]
  42     rw_byte_mask = Signal(4, name="memory_interface_rw_byte_mask")
  43     rw_read_not_write = Signal(name="memory_interface_rw_read_not_write")
  44     rw_active = Signal(name="memory_interface_rw_active")
  45     rw_data_in = Signal(32, name="memory_interface_rw_data_in")
  46     rw_data_out = Signal(32, name="memory_interface_rw_data_out")
  47     rw_address_valid = Signal(name="memory_interface_rw_address_valid")
  48     rw_wait = Signal(name="memory_interface_rw_wait")
  49
  50
  51 class Decoder:
  52     funct7 = Signal(7, name="decoder_funct7")
  53     funct3 = Signal(3, name="decoder_funct3")
  54     rd = Signal(5, name="decoder_rd")
  55     rs1 = Signal(5, name="decoder_rs1")
  56     rs2 = Signal(5, name="decoder_rs2")
  57     immediate = Signal(32, name="decoder_immediate")
  58     opcode = Signal(7, name="decoder_opcode")
  59     act = Signal(decode_action, name="decoder_action")
  60
  61
  62 class MStatus:
  63     def __init__(self, comb, sync):
  64         self.comb = comb
  65         self.sync = sync
  66         self.mpie = Signal(name="mstatus_mpie")
  67         self.mie = Signal(name="mstatus_mie")
  68         self.mstatus = Signal(32, name="mstatus")
  69
  70         self.sync += self.mie.eq(0)
  71         self.sync += self.mpie.eq(0)
  72         self.sync += self.mstatus.eq(0)
  73
  74
  75 class MIE:
  76     def __init__(self, comb, sync):
  77         self.comb = comb
  78         self.sync = sync
  79         self.meie = Signal(name="mie_meie")
  80         self.mtie = Signal(name="mie_mtie")
  81         self.msie = Signal(name="mie_msie")
  82         self.mie = Signal(32)
  83
  84
  85 class MIP:
  86     def __init__(self):
  87         self.mip = Signal(32)
  88
  89
  90 class M:
  91     def __init__(self, comb, sync):
  92         self.comb = comb
  93         self.sync = sync
  94         self.mcause = Signal(32)
  95         self.mepc = Signal(32)
  96         self.mscratch = Signal(32)
  97         self.sync += self.mcause.eq(0)
  98         self.sync += self.mepc.eq(0) # 32'hXXXXXXXX;
  99         self.sync += self.mscratch.eq(0) # 32'hXXXXXXXX;
 100
 101
 102 class Misa:
 103     def __init__(self, comb, sync):
 104         self.comb = comb
 105         self.sync = sync
 106         self.misa = Signal(32)
 107         cl = []
 108         for l in list(string.ascii_lowercase):
 109             value = 1 if l == 'i' else 0
 110             cl.append(Constant(value))
 111         cl.append(Constant(0, 4))
 112         cl.append(Constant(0b01, 2))
 113         self.comb += self.misa.eq(Cat(cl))
 114
 115
 116 class Fetch:
 117     def __init__(self, comb, sync):
 118         self.comb = comb
 119         self.sync = sync
 120         self.action = Signal(fetch_action, name="fetch_action")
 121         self.target_pc = Signal(32, name="fetch_target_pc")
 122         self.output_pc = Signal(32, name="fetch_output_pc")
 123         self.output_instruction = Signal(32, name="fetch_ouutput_instruction")
 124         self.output_state = Signal(fetch_output_state,name="fetch_output_state")
 125
 126 class CSR:
 127     def __init__(self, comb, sync, dc, register_rs1):
 128         self.comb = comb
 129         self.sync = sync
 130         self.number = Signal(12, name="csr_number")
 131         self.input_value = Signal(32, name="csr_input_value")
 132         self.reads = Signal(name="csr_reads")
 133         self.writes = Signal(name="csr_writes")
 134         self.op_is_valid = Signal(name="csr_op_is_valid")
 135
 136         self.comb += self.number.eq(dc.immediate)
 137         self.comb += self.input_value.eq(Mux(dc.funct3[2],
 138                                             dc.rs1,
 139                                             register_rs1))
 140         self.comb += self.reads.eq(dc.funct3[1] | (dc.rd != 0))
 141         self.comb += self.writes.eq(~dc.funct3[1] | (dc.rs1 != 0))
 142
 143         self.comb += self.get_csr_op_is_valid()
 144
 145     def get_csr_op_is_valid(self):
 146         """ determines if a CSR is valid
 147         """
 148         c = {}
 149         # invalid csrs
 150         for f in [csr_ustatus, csr_fflags, csr_frm, csr_fcsr,
 151                   csr_uie, csr_utvec, csr_uscratch, csr_uepc,
 152                   csr_ucause, csr_utval, csr_uip, csr_sstatus,
 153                   csr_sedeleg, csr_sideleg, csr_sie, csr_stvec,
 154                   csr_scounteren, csr_sscratch, csr_sepc, csr_scause,
 155                   csr_stval, csr_sip, csr_satp, csr_medeleg,
 156                   csr_mideleg, csr_dcsr, csr_dpc, csr_dscratch]:
 157             c[f] = self.op_is_valid.eq(0)
 158
 159         # not-writeable -> ok
 160         for f in [csr_cycle, csr_time, csr_instret, csr_cycleh,
 161                   csr_timeh, csr_instreth, csr_mvendorid, csr_marchid,
 162                   csr_mimpid, csr_mhartid]:
 163             c[f] = self.op_is_valid.eq(~self.writes)
 164
 165         # valid csrs
 166         for f in [csr_misa, csr_mstatus, csr_mie, csr_mtvec,
 167                   csr_mscratch, csr_mepc, csr_mcause, csr_mip]:
 168             c[f] = self.op_is_valid.eq(1)
 169
 170         # not implemented / default
 171         for f in [csr_mcounteren, csr_mtval, csr_mcycle, csr_minstret,
 172                   csr_mcycleh, csr_minstreth, "default"]:
 173             c[f] = self.op_is_valid.eq(0)
 174
 175         return Case(self.number, c)
 176
 177     def evaluate_csr_funct3_op(self, funct3, previous, written):
 178         c = { "default": written.eq(Constant(0, 32))}
 179         for f in [F3.csrrw, F3.csrrwi]:
 180             c[f] = written.eq(self.input_value)
 181         for f in [F3.csrrs, F3.csrrsi]:
 182             c[f] = written.eq(self.input_value | previous)
 183         for f in [F3.csrrc, F3.csrrci]:
 184             c[f] = written.eq(~self.input_value & previous)
 185         return Case(funct3, c)
 186
 187
 188 class MInfo:
 189     def __init__(self, comb):
 190         self.comb = comb
 191         # TODO
 192         self.cycle_counter   = Signal(64); # TODO: implement cycle_counter
 193         self.time_counter    = Signal(64); # TODO: implement time_counter
 194         self.instret_counter = Signal(64); # TODO: implement instret_counter
 195
 196         self.mvendorid = Signal(32)
 197         self.marchid = Signal(32)
 198         self.mimpid = Signal(32)
 199         self.mhartid = Signal(32)
 200         self.comb += self.mvendorid.eq(Constant(0, 32))
 201         self.comb += self.marchid.eq(Constant(0, 32))
 202         self.comb += self.mimpid.eq(Constant(0, 32))
 203         self.comb += self.mhartid.eq(Constant(0, 32))
 204
 205 class Regs:
 206     def __init__(self, comb, sync):
 207         self.comb = comb
 208         self.sync = sync
 209
 210         self.ra_en = Signal(reset=1, name="regfile_ra_en") # TODO: ondemand en
 211         self.rs1 = Signal(32, name="regfile_rs1")
 212         self.rs_a = Signal(5, name="regfile_rs_a")
 213
 214         self.rb_en = Signal(reset=1, name="regfile_rb_en") # TODO: ondemand en
 215         self.rs2 = Signal(32, name="regfile_rs2")
 216         self.rs_b = Signal(5, name="regfile_rs_b")
 217
 218         self.w_en = Signal(name="regfile_w_en")
 219         self.wval = Signal(32, name="regfile_wval")
 220         self.rd = Signal(32, name="regfile_rd")
 221
 222 class CPU(Module):
 223     """
 224     """
 225
 226     def get_lsbm(self, dc):
 227         return Cat(Constant(1),
 228                    Mux((dc.funct3[1] | dc.funct3[0]),
 229                        Constant(1), Constant(0)),
 230                    Mux((dc.funct3[1]),
 231                        Constant(0b11, 2), Constant(0, 2)))
 232
 233     # XXX this happens to get done by various self.sync actions
 234     #def reset_to_initial(self, m, mstatus, mie, registers):
 235     #    return [m.mcause.eq(0),
 236     #            ]
 237
 238     def main_block(self, mtvec, mip, minfo, misa, csr, mi, m, mstatus, mie,
 239                          ft, dc,
 240                          load_store_misaligned,
 241                          loaded_value, alu_result,
 242                          lui_auipc_result):
 243         c = {}
 244         c[FOS.empty] = []
 245         c[FOS.trap] = self.handle_trap.eq(1)
 246         c[FOS.valid] = self.handle_valid(mtvec, mip, minfo, misa, csr, mi, m,
 247                                        mstatus, mie, ft, dc,
 248                                        load_store_misaligned,
 249                                        loaded_value,
 250                                        alu_result,
 251                                        lui_auipc_result)
 252         return [self.handle_trap.eq(0),
 253                 self.regs.w_en.eq(0),
 254                 Case(ft.output_state, c),
 255                 self.handle_trap.eq(0),
 256                 self.regs.w_en.eq(0)]
 257
 258     def write_register(self, rd, val):
 259         return [self.regs.rd.eq(rd),
 260                 self.regs.wval.eq(val),
 261                 self.regs.w_en.eq(1)
 262                ]
 263
 264     def handle_valid(self, mtvec, mip, minfo, misa, csr, mi, m, mstatus, mie,
 265                            ft, dc,
 266                            load_store_misaligned,
 267                            loaded_value, alu_result,
 268                            lui_auipc_result):
 269         # fetch action ack trap
 270         i = If((ft.action == FA.ack_trap) | (ft.action == FA.noerror_trap),
 271                 [self.handle_trap.eq(1),
 272                 ]
 273               )
 274
 275         # load
 276         i = i.Elif((dc.act & DA.load) != 0,
 277                 If(~mi.rw_wait,
 278                     self.write_register(dc.rd, loaded_value)
 279                 )
 280               )
 281
 282         # op or op_immediate
 283         i = i.Elif((dc.act & DA.op_op_imm) != 0,
 284                 self.write_register(dc.rd, alu_result)
 285               )
 286
 287         # lui or auipc
 288         i = i.Elif((dc.act & DA.lui_auipc) != 0,
 289                 self.write_register(dc.rd, lui_auipc_result)
 290               )
 291
 292         # jal/jalr
 293         i = i.Elif((dc.act & (DA.jal | DA.jalr)) != 0,
 294                 self.write_register(dc.rd, ft.output_pc + 4)
 295               )
 296
 297         i = i.Elif((dc.act & DA.csr) != 0,
 298                 self.handle_csr(mtvec, mip, minfo, misa, mstatus, mie, m,
 299                                 dc, csr)
 300               )
 301
 302         # fence, store, branch
 303         i = i.Elif((dc.act & (DA.fence | DA.fence_i |
 304                               DA.store | DA.branch)) != 0,
 305                 # do nothing
 306               )
 307
 308         return i
 309
 310     def handle_csr(self, mtvec, mip, minfo, misa, mstatus, mie, m, dc, csr):
 311         csr_output_value = Signal(32)
 312         csr_written_value = Signal(32)
 313         c = {}
 314
 315         # cycle
 316         c[csr_cycle]  = csr_output_value.eq(minfo.cycle_counter[0:32])
 317         c[csr_cycleh] = csr_output_value.eq(minfo.cycle_counter[32:64])
 318         # time
 319         c[csr_time]  = csr_output_value.eq(minfo.time_counter[0:32])
 320         c[csr_timeh] = csr_output_value.eq(minfo.time_counter[32:64])
 321         # instret
 322         c[csr_instret]  = csr_output_value.eq(minfo.instret_counter[0:32])
 323         c[csr_instreth] = csr_output_value.eq(minfo.instret_counter[32:64])
 324         # mvendorid/march/mimpl/mhart
 325         c[csr_mvendorid] = csr_output_value.eq(minfo.mvendorid)
 326         c[csr_marchid  ] = csr_output_value.eq(minfo.marchid  )
 327         c[csr_mimpid   ] = csr_output_value.eq(minfo.mimpid   )
 328         c[csr_mhartid  ] = csr_output_value.eq(minfo.mhartid  )
 329         # misa
 330         c[csr_misa     ] = csr_output_value.eq(misa.misa)
 331         # mstatus
 332         c[csr_mstatus  ] = [
 333             csr_output_value.eq(mstatus.mstatus),
 334             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
 335                                                   csr_written_value),
 336             mstatus.mpie.eq(csr_written_value[7]),
 337             mstatus.mie.eq(csr_written_value[3])
 338         ]
 339         # mie
 340         c[csr_mie      ] = [
 341             csr_output_value.eq(mie.mie),
 342             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
 343                                                   csr_written_value),
 344             mie.meie.eq(csr_written_value[11]),
 345             mie.mtie.eq(csr_written_value[7]),
 346             mie.msie.eq(csr_written_value[3]),
 347         ]
 348         # mtvec
 349         c[csr_mtvec    ] = csr_output_value.eq(mtvec)
 350         # mscratch
 351         c[csr_mscratch ] = [
 352             csr_output_value.eq(m.mscratch),
 353             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
 354                                                   csr_written_value),
 355             If(csr.writes,
 356                 m.mscratch.eq(csr_written_value),
 357             )
 358         ]
 359         # mepc
 360         c[csr_mepc ] = [
 361             csr_output_value.eq(m.mepc),
 362             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
 363                                                   csr_written_value),
 364             If(csr.writes,
 365                 m.mepc.eq(csr_written_value),
 366             )
 367         ]
 368
 369         # mcause
 370         c[csr_mcause ] = [
 371             csr_output_value.eq(m.mcause),
 372             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
 373                                                   csr_written_value),
 374             If(csr.writes,
 375                 m.mcause.eq(csr_written_value),
 376             )
 377         ]
 378
 379         # mip
 380         c[csr_mip  ] = [
 381             csr_output_value.eq(mip.mip),
 382             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
 383                                                   csr_written_value),
 384         ]
 385
 386         return [Case(csr.number, c),
 387                 If(csr.reads,
 388                     self.write_register(dc.rd, csr_output_value)
 389                 )]
 390
 391     def __init__(self):
 392         Module.__init__(self)
 393         self.clk = ClockSignal()
 394         self.reset = ResetSignal()
 395         self.tty_write = Signal()
 396         self.tty_write_data = Signal(8)
 397         self.tty_write_busy = Signal()
 398         self.switch_2 = Signal()
 399         self.switch_3 = Signal()
 400         self.led_1 = Signal()
 401         self.led_3 = Signal()
 402
 403         ram_size = Constant(0x8000)
 404         ram_start = Constant(0x10000, 32)
 405         reset_vector = Signal(32)
 406         mtvec = Signal(32)
 407
 408         reset_vector.eq(ram_start)
 409         mtvec.eq(ram_start + 0x40)
 410
 411         self.regs = Regs(self.comb, self.sync)
 412
 413         rf = Instance("RegFile", name="regfile",
 414            i_ra_en = self.regs.ra_en,
 415            i_rb_en = self.regs.rb_en,
 416            i_w_en = self.regs.w_en,
 417            o_read_a = self.regs.rs1,
 418            o_read_b = self.regs.rs2,
 419            i_writeval = self.regs.wval,
 420            i_rs_a = self.regs.rs_a,
 421            i_rs_b = self.regs.rs_b,
 422            i_rd = self.regs.rd)
 423
 424         self.specials += rf
 425
 426         mi = MemoryInterface()
 427
 428         mii = Instance("cpu_memory_interface", name="memory_instance",
 429                     p_ram_size = ram_size,
 430                     p_ram_start = ram_start,
 431                     i_clk=ClockSignal(),
 432                     i_rst=ResetSignal(),
 433                     i_fetch_address = mi.fetch_address,
 434                     o_fetch_data = mi.fetch_data,
 435                     o_fetch_valid = mi.fetch_valid,
 436                     i_rw_address = mi.rw_address,
 437                     i_rw_byte_mask = mi.rw_byte_mask,
 438                     i_rw_read_not_write = mi.rw_read_not_write,
 439                     i_rw_active = mi.rw_active,
 440                     i_rw_data_in = mi.rw_data_in,
 441                     o_rw_data_out = mi.rw_data_out,
 442                     o_rw_address_valid = mi.rw_address_valid,
 443                     o_rw_wait = mi.rw_wait,
 444                     o_tty_write = self.tty_write,
 445                     o_tty_write_data = self.tty_write_data,
 446                     i_tty_write_busy = self.tty_write_busy,
 447                     i_switch_2 = self.switch_2,
 448                     i_switch_3 = self.switch_3,
 449                     o_led_1 = self.led_1,
 450                     o_led_3 = self.led_3
 451                   )
 452         self.specials += mii
 453
 454         ft = Fetch(self.comb, self.sync)
 455
 456         fs = Instance("CPUFetchStage", name="fetch_stage",
 457             i_clk=ClockSignal(),
 458             i_rst=ResetSignal(),
 459             o_memory_interface_fetch_address = mi.fetch_address,
 460             i_memory_interface_fetch_data = mi.fetch_data,
 461             i_memory_interface_fetch_valid = mi.fetch_valid,
 462             i_fetch_action = ft.action,
 463             i_target_pc = ft.target_pc,
 464             o_output_pc = ft.output_pc,
 465             o_output_instruction = ft.output_instruction,
 466             o_output_state = ft.output_state,
 467             i_reset_vector = reset_vector,
 468             i_mtvec = mtvec,
 469         )
 470         self.specials += fs
 471
 472         dc = Decoder()
 473
 474         cd = Instance("CPUDecoder", name="decoder",
 475             i_instruction = ft.output_instruction,
 476             o_funct7 = dc.funct7,
 477             o_funct3 = dc.funct3,
 478             o_rd = dc.rd,
 479             o_rs1 = dc.rs1,
 480             o_rs2 = dc.rs2,
 481             o_immediate = dc.immediate,
 482             o_opcode = dc.opcode,
 483             o_decode_action = dc.act
 484         )
 485         self.specials += cd
 486
 487         self.comb += self.regs.rs_a.eq(dc.rs1)
 488         self.comb += self.regs.rs_b.eq(dc.rs2)
 489
 490         load_store_address = Signal(32)
 491         load_store_address_low_2 = Signal(2)
 492         load_store_misaligned = Signal()
 493         unmasked_loaded_value = Signal(32)
 494         loaded_value = Signal(32)
 495
 496         lsc = Instance("CPULoadStoreCalc", name="cpu_loadstore_calc",
 497             i_dc_immediate = dc.immediate,
 498             i_dc_funct3 = dc.funct3,
 499             i_rs1 = self.regs.rs1,
 500             i_rs2 = self.regs.rs2,
 501             i_rw_data_in = mi.rw_data_in,
 502             i_rw_data_out = mi.rw_data_out,
 503             o_load_store_address = load_store_address,
 504             o_load_store_address_low_2 = load_store_address_low_2,
 505             o_load_store_misaligned = load_store_misaligned,
 506             o_loaded_value = loaded_value)
 507
 508         self.specials += lsc
 509
 510         # XXX rwaddr not 31:2 any more
 511         self.comb += mi.rw_address.eq(load_store_address[2:])
 512
 513         unshifted_load_store_byte_mask = Signal(4)
 514
 515         self.comb += unshifted_load_store_byte_mask.eq(self.get_lsbm(dc))
 516
 517         # XXX yuck.  this will cause migen simulation to fail
 518         # (however conversion to verilog works)
 519         self.comb += mi.rw_byte_mask.eq(
 520                 _Operator("<<", [unshifted_load_store_byte_mask,
 521                                         load_store_address_low_2]))
 522
 523         self.comb += mi.rw_active.eq(~self.reset
 524                         & (ft.output_state == FOS.valid)
 525                         & ~load_store_misaligned
 526                         & ((dc.act & (DA.load | DA.store)) != 0))
 527
 528         self.comb += mi.rw_read_not_write.eq(~dc.opcode[5])
 529
 530         # alu
 531         alu_a = Signal(32)
 532         alu_b = Signal(32)
 533         alu_result = Signal(32)
 534
 535         self.comb += alu_a.eq(self.regs.rs1)
 536         self.comb += alu_b.eq(Mux(dc.opcode[5],
 537                                   self.regs.rs2,
 538                                   dc.immediate))
 539
 540         ali = Instance("cpu_alu", name="alu",
 541             i_funct7 = dc.funct7,
 542             i_funct3 = dc.funct3,
 543             i_opcode = dc.opcode,
 544             i_a = alu_a,
 545             i_b = alu_b,
 546             o_result = alu_result
 547         )
 548         self.specials += ali
 549
 550         lui_auipc_result = Signal(32)
 551         self.comb += lui_auipc_result.eq(Mux(dc.opcode[5],
 552                                              dc.immediate,
 553                                              dc.immediate + ft.output_pc))
 554
 555         self.comb += ft.target_pc.eq(Cat(0,
 556                     Mux(dc.opcode != OP.jalr,
 557                                 ft.output_pc[1:32],
 558                                 self.regs.rs1[1:32] + dc.immediate[1:32])))
 559
 560         misaligned_jump_target = Signal()
 561         self.comb += misaligned_jump_target.eq(ft.target_pc[1])
 562
 563         branch_arg_a = Signal(32)
 564         branch_arg_b = Signal(32)
 565         self.comb += branch_arg_a.eq(Cat( self.regs.rs1[0:31],
 566                                           self.regs.rs1[31] ^ ~dc.funct3[1]))
 567         self.comb += branch_arg_b.eq(Cat( self.regs.rs2[0:31],
 568                                           self.regs.rs2[31] ^ ~dc.funct3[1]))
 569
 570         branch_taken = Signal()
 571         self.comb += branch_taken.eq(dc.funct3[0] ^
 572                                      Mux(dc.funct3[2],
 573                                          branch_arg_a < branch_arg_b,
 574                                          branch_arg_a == branch_arg_b))
 575
 576         m = M(self.comb, self.sync)
 577         mstatus = MStatus(self.comb, self.sync)
 578         mie = MIE(self.comb, self.sync)
 579         misa = Misa(self.comb, self.sync)
 580         mip = MIP()
 581
 582         mp = Instance("CPUMIP", name="cpu_mip",
 583             o_mip = mip.mip)
 584
 585         self.specials += mp
 586
 587         mii = Instance("CPUMIE", name="cpu_mie",
 588             o_mie = mie.mie,
 589             i_meie = mie.meie,
 590             i_mtie = mie.mtie,
 591             i_msie = mie.msie)
 592
 593         self.specials += mii
 594
 595         ms = Instance("CPUMStatus", name="cpu_mstatus",
 596             o_mstatus = mstatus.mstatus,
 597             i_mpie = mstatus.mpie,
 598             i_mie = mstatus.mie)
 599
 600         self.specials += ms
 601
 602         # CSR decoding
 603         csr = CSR(self.comb, self.sync, dc, self.regs.rs1)
 604
 605         fi = Instance("CPUFetchAction", name="cpu_fetch_action",
 606             o_fetch_action = ft.action,
 607             i_output_state = ft.output_state,
 608             i_dc_act = dc.act,
 609             i_load_store_misaligned = load_store_misaligned,
 610             i_mi_rw_wait = mi.rw_wait,
 611             i_mi_rw_address_valid = mi.rw_address_valid,
 612             i_branch_taken = branch_taken,
 613             i_misaligned_jump_target = misaligned_jump_target,
 614             i_csr_op_is_valid = csr.op_is_valid)
 615
 616         self.specials += fi
 617
 618         minfo = MInfo(self.comb)
 619
 620         self.handle_trap = Signal(reset=0)
 621
 622         ht = Instance("CPUHandleTrap", "cpu_handle_trap",
 623                       i_ft_action = ft.action,
 624                       i_ft_output_pc = ft.output_pc,
 625                       i_dc_action = dc.act,
 626                       i_dc_immediate = dc.immediate,
 627                       i_load_store_misaligned = load_store_misaligned,
 628                       o_mcause = m.mcause,
 629                       o_mepc = m.mepc,
 630                       o_mie = mstatus.mie)
 631
 632         self.specials += ht
 633
 634         self.sync += If(~self.reset,
 635                         self.main_block(mtvec, mip, minfo, misa, csr, mi, m,
 636                                         mstatus, mie, ft, dc,
 637                                         load_store_misaligned,
 638                                         loaded_value,
 639                                        alu_result,
 640                                        lui_auipc_result)
 641                      )
 642
 643 if __name__ == "__main__":
 644     example = CPU()
 645     print(verilog.convert(example,
 646          {
 647            example.tty_write,
 648            example.tty_write_data,
 649            example.tty_write_busy,
 650            example.switch_2,
 651            example.switch_3,
 652            example.led_1,
 653            example.led_3,
 654            }))