src/main/scala/util/RegMapFIFO.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.util
   3
   4 import Chisel._
   5 import freechips.rocketchip.regmapper._
   6
   7 // MSB indicates full status
   8 object NonBlockingEnqueue {
   9   def apply(enq: DecoupledIO[UInt], regWidth: Int = 32): Seq[RegField] = {
  10     val enqWidth = enq.bits.getWidth
  11     val quash = Wire(Bool())
  12     require(enqWidth > 0)
  13     require(regWidth > enqWidth)
  14     Seq(
  15       RegField(enqWidth,
  16         RegReadFn(UInt(0)),
  17         RegWriteFn((valid, data) => {
  18           enq.valid := valid && !quash
  19           enq.bits := data
  20           Bool(true)
  21         })),
  22       RegField(regWidth - enqWidth - 1),
  23       RegField(1,
  24         !enq.ready,
  25         RegWriteFn((valid, data) =>  {
  26           quash := valid && data(0)
  27           Bool(true)
  28         })))
  29   }
  30 }
  31
  32 // MSB indicates empty status
  33 object NonBlockingDequeue {
  34   def apply(deq: DecoupledIO[UInt], regWidth: Int = 32): Seq[RegField] = {
  35     val deqWidth = deq.bits.getWidth
  36     require(deqWidth > 0)
  37     require(regWidth > deqWidth)
  38     Seq(
  39       RegField.r(deqWidth,
  40         RegReadFn(ready => {
  41           deq.ready := ready
  42           (Bool(true), deq.bits)
  43         })),
  44       RegField(regWidth - deqWidth - 1),
  45       RegField.r(1, !deq.valid))
  46   }
  47 }