Merge pull request #27 from sifive/typed_pad_ctrl

[sifive-blocks.git] / src / main / scala / devices / gpio / JTAG.scala

diff --git a/src/main/scala/devices/gpio/JTAG.scala b/src/main/scala/devices/gpio/JTAG.scala
deleted file mode 100644 (file)
index 63d9cc2..0000000
--- a/src/main/scala/devices/gpio/JTAG.scala
+++ /dev/null
@@ -1,41 +0,0 @@
-// See LICENSE for license details.
-package sifive.blocks.devices.gpio
-
-import Chisel._
-
-// ------------------------------------------------------------
-// SPI, UART, etc are with their
-// respective packages,
-// This file is for those that don't seem to have a good place
-// to put them otherwise.
-// ------------------------------------------------------------
-
-import freechips.rocketchip.config._
-import freechips.rocketchip.jtag.{JTAGIO}
-
-class JTAGPinsIO(hasTRSTn: Boolean = true) extends Bundle {
-
-  val TCK    = new GPIOPin()
-  val TMS    = new GPIOPin()
-  val TDI    = new GPIOPin()
-  val TDO    = new GPIOPin()
-  val TRSTn  = if (hasTRSTn) Option(new GPIOPin()) else None
-
-}
-
-class JTAGGPIOPort(hasTRSTn: Boolean = true)(implicit p: Parameters) extends Module {
-
-  val io = new Bundle {
-    // TODO: make this not hard-coded true.
-    val jtag = new JTAGIO(hasTRSTn)
-    val pins = new JTAGPinsIO(hasTRSTn)
-  }
-
-  io.jtag.TCK  := GPIOInputPinCtrl(io.pins.TCK, pue = Bool(true)).asClock
-  io.jtag.TMS  := GPIOInputPinCtrl(io.pins.TMS, pue = Bool(true))
-  io.jtag.TDI  := GPIOInputPinCtrl(io.pins.TDI, pue = Bool(true))
-  io.jtag.TRSTn.foreach{t => t := GPIOInputPinCtrl(io.pins.TRSTn.get, pue = Bool(true))}
-
-  GPIOOutputPinCtrl(io.pins.TDO, io.jtag.TDO.data)
-  io.pins.TDO.o.oe := io.jtag.TDO.driven
-}