package sifive.blocks.devices.mockaon
import Chisel._
+import config.Field
+import coreplex.CoreplexRISCVPlatform
import diplomacy.LazyModule
-import rocketchip.{TopNetwork,TopNetworkModule}
+import rocketchip.{
+ HasTopLevelNetworks,
+ HasTopLevelNetworksBundle,
+ HasTopLevelNetworksModule
+}
import uncore.tilelink2.{IntXing, TLAsyncCrossingSource, TLFragmenter}
-import coreplex._
-trait PeripheryMockAON extends TopNetwork {
- val mockAONConfig: MockAONConfig
+case object PeripheryMockAONKey extends Field[MockAONParams]
+
+trait HasPeripheryMockAON extends HasTopLevelNetworks {
val coreplex: CoreplexRISCVPlatform
// We override the clock & Reset here so that all synchronizers, etc
// are in the proper clock domain.
- val aon = LazyModule(new MockAONWrapper(mockAONConfig))
+ val mockAONParams= p(PeripheryMockAONKey)
+ val aon = LazyModule(new MockAONWrapper(peripheryBusBytes, mockAONParams))
val aon_int = LazyModule(new IntXing)
- aon.node := TLAsyncCrossingSource()(TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node))
+ aon.node := TLAsyncCrossingSource()(TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node))
aon_int.intnode := aon.intnode
intBus.intnode := aon_int.intnode
}
-trait PeripheryMockAONBundle {
+trait HasPeripheryMockAONBundle extends HasTopLevelNetworksBundle {
val aon = new MockAONWrapperBundle()
}
-trait PeripheryMockAONModule {
- this: TopNetworkModule {
- val outer: PeripheryMockAON
- val io: PeripheryMockAONBundle
- } =>
+trait HasPeripheryMockAONModule extends HasTopLevelNetworksModule {
+ val outer: HasPeripheryMockAON
+ val io: HasPeripheryMockAONBundle
io.aon <> outer.aon.module.io