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spi: SPIParamsBase param needs to be public
[sifive-blocks.git]
/
src
/
main
/
scala
/
ip
/
xilinx
/
vc707mig
/ vc707mig.scala
2017-08-18
Shreesha Srinath
Merge pull request #34 from ss2783/master
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2017-08-18
Shreesha Srinath
Updates to go with the fpga-shells directory
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2017-07-07
Henry Cook
Refactor package hierarchy. (#25)
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2017-05-13
Wesley W. Terpstra
Merge pull request #14 from sifive/async-pcie
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2017-05-13
Wesley W. Terpstra
vc707mig: use an external ibuf
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2017-04-25
Henry Styles
Merge pull request #9 from sifive/vc707_mig_analog_inout
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2017-04-25
Henry Styles
Use _chisel3 analog for MIG inout
vc707_mig_analog_inout
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2016-11-29
SiFive
Initial commit.
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