reduce TLB set size from 64 to 16 to get FPGA resource utilisation down
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 18 Feb 2022 11:53:06 +0000 (11:53 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 18 Feb 2022 11:53:06 +0000 (11:53 +0000)
commit88a7bb476664778400e29a5c1b929fa9a2d74cd6
tree39979b36445fbf8f2fb7ed8a410fa1d0783cbe1d
parentfe447fa66a111bb213b76a8bdc544d154944d3fc
reduce TLB set size from 64 to 16 to get FPGA resource utilisation down
Makefile
src/soc/experiment/dcache.py
src/soc/experiment/icache.py