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(parent: 2b0ca12) | patch
pass over store_done correctly from dcache over PortInterface
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 16 Jan 2022 16:28:49 +0000 (16:28 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 16 Jan 2022 16:28:49 +0000 (16:28 +0000)
commit08da1aa61af77093c34cfa9f57ad47641c9999b4
tree204e484733e43b6e1e2d1ee4eabd352f4e6a4db6tree
parent2b0ca1269a83ac1fb9b58be47800d2041b3c694ccommit | diff
pass over store_done correctly from dcache over PortInterface
into LDSTCompUnit so that it can set CR0 correctly on stdcx. etc.
src/soc/experiment/compldst_multi.py diff | blob | history
src/soc/experiment/pimem.py diff | blob | history
src/soc/fu/ldst/loadstore.py diff | blob | history