big rename, global/search/replace of ready_o with o_ready and the other
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 24 Aug 2021 10:22:14 +0000 (11:22 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 24 Aug 2021 10:22:14 +0000 (11:22 +0100)
commit157669066b9990ca430f49293bcd97f9ae51890d
treea8d65691d7635f26b6599c412715faa662ba1211
parentcb49428fe0347ec2a939f884e8fe3e5d2b1eae21
big rename, global/search/replace of ready_o with o_ready and the other
> 4 signals as well, valid_i -> i_valid
> https://libera.irclog.whitequark.org/nmigen/2021-08-24#30728292;
> to be consistent with nmigen standards
27 files changed:
src/soc/config/test/test_fetch.py
src/soc/config/test/test_loadstore.py
src/soc/experiment/alu_fsm.py
src/soc/experiment/alu_hier.py
src/soc/experiment/compalu.py
src/soc/experiment/compalu_multi.py
src/soc/experiment/dcache.py
src/soc/experiment/formal/proof_alu_fsm.py
src/soc/experiment/imem.py
src/soc/experiment/lsmem.py
src/soc/experiment/pi2ls.py
src/soc/experiment/score6600.py
src/soc/experiment/score6600_multi.py
src/soc/experiment/test/test_compalu_multi.py
src/soc/fu/compunits/formal/proof_fu.py
src/soc/fu/div/fsm.py
src/soc/fu/mmu/fsm.py
src/soc/minerva/units/fetch.py
src/soc/minerva/units/loadstore.py
src/soc/scoreboard/addr_split.py
src/soc/scoreboard/fn_unit.py
src/soc/scoreboard/instruction_q.py
src/soc/scoreboard/test_iq.py
src/soc/simple/core.py
src/soc/simple/issuer.py
src/soc/simple/test/test_core.py
src/soc/simple/test/test_runner.py