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(parent: fc0f99a) | patch
sigh, monitor DEC/TB StateRegs "properly" so that the Issuer DEC/TB FSM
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 21 Jan 2022 00:12:39 +0000 (00:12 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 21 Jan 2022 00:12:39 +0000 (00:12 +0000)
commit506157e41e93edcfdbc95f2f8f38b371cdf09332
tree444b8fb1cdaf4b9f47c39b9a9336f7d600c1f542tree
parentfc0f99a9398cf638c509bd68d1533d1dd701268dcommit | diff
sigh, monitor DEC/TB StateRegs "properly" so that the Issuer DEC/TB FSM
does not end up in a race condition with the SPR pipeline for writing
to DEC or TB
src/soc/simple/core.py diff | blob | history
src/soc/simple/issuer.py diff | blob | history