good grief, finally tracked down a piece of missing code in the MMU

good grief, finally tracked down a piece of missing code in the MMU
address-shift had somehow not been included
@@ -509,6 +523,10 @@ class MMU(Elaboratable):
         comb += tlb_mask.shift.eq(r.shift)
         comb += finalmask.eq(tlb_mask.mask)

+        # Shift address bits 61--12 right by 0--47 bits and
+        # supply the least significant 16 bits of the result.
+        comb += addrsh.eq(r.addr[12:62] << r.shift)
+

microwatt mmu.bin test 2 should now succeed